Rainer Kress

Publication Activity (10 Years)

Years Active: 1992-2014
Publications (10 Years): 0

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DATE

Kaiserslautern University of Technology, Germany (PHD)

Education History

Kaiserslautern University of Technology, Germany

PHD

Publications

Marco Casale-Rossi, Pietro Palella, Mario Anton, Ori Galzur, Robert Hum, Rainer Kress, Paul Lo
Panel: The world is going... analog & mixed-signal! What about EDA? DATE (2014)
Marco Casale-Rossi, Pierluigi Rolandi, Andreas Bruening, Antun Domic, Rainer Kress, Joseph Sawicki, Christian Sebeke
Panel: What is EDA doing for trailing edge technologies? DATE (2012)
Michael Mrva, Rainer Kress
Role-Centered Conceptual Modeling in System Design. MBMV (2000)
Rainer Kress, Andreas Pyttel, Alexander Sedlmeier
FPGA-Based Prototyping for Product Definition. FPL (2000)
Rainer Kress, Andreas Pyttel
Debugging Application-Specific Programmable Products. FPL (1999)
Josef Fleischmann, Klaus Buchenrieder, Rainer Kress
Java Driven Codesign and Prototyping of Networked Embedded Systems. DAC (1999)
Josef Fleischmann, Klaus Buchenrieder, Rainer Kress
Codesign of Embedded Systems Based on Java and Reconfigurable Hardware Components. DATE (1999)
Rainer Kress, Andreas Pyttel
High-Level Synthesis for Dynamically Reconfigurable Hardware/Software Systems. FPL (1998)
Josef Fleischmann, Klaus Buchenrieder, Rainer Kress
A hardware/software prototyping environment for dynamically reconfigurable embedded systems. CODES (1998)
Michael Mrva, Klaus Buchenrieder, Rainer Kress
A Scalable Architecture for Multi-threaded JAVA Applications. DATE (1998)
Rainer Kress, Reiner W. Hartenstein, Ulrich Nageldinger
An operating system for custom computing machines based on the Xputer paradigm. FPL (1997)
Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Rainer Kress, Ulrich Nageldinger
A Partitioning Programming Environment for a Novel Parallel Architecture. IPPS (1996)
Reiner W. Hartenstein, Jürgen Becker, Rainer Kress
Two-level Partitioning of Image Processing Algorithms for the Parallel Map-oriented Machine. CODES (1996)
Reiner W. Hartenstein, Jürgen Becker, Rainer Kress
Two-Level Hardware/Software Partitioning Using CoDe-X. ECBS (1996)
Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig
High-performance computing using a reconfigurable accelerator. Concurr. Pract. Exp. 8 (6) (1996)
Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig
CoDe-C: A Novel Two-Level Hardware/Software Co-Design Framework. VLSI Design (1996)
Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Rainer Kress, Ulrich Nageldinger
A Synthesis System For Bus-Based Wavefront Array Architectures. ASAP (1996)
Reiner W. Hartenstein, Jürgen Becker, Rainer Kress
An Embedded Accelerator for Real-Time Image Processing. RTS (1996)
Reiner W. Hartenstein, Jürgen Becker, Rainer Kress
Custom Computing Machines vs. Hardware/Software Codesign: From a globalized point of view. FPL (1996)
Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig, Karin Schmidt
A Parallelizing Compilation Method for the Map-oriented Machine. ASAP (1995)
Reiner W. Hartenstein, Rainer Kress
A datapath synthesis system for the reconfigurable datapath architecture. ASP-DAC (1995)
Reiner W. Hartenstein, Rainer Kress, Helmut Reinig
A New FPGA Architecture for Word-Oriented Datapaths. FPL (1994)
Reiner W. Hartenstein, Rainer Kress, Helmut Reinig
A dynamically reconfigurable wavefront array architecture for evaluation of expressions. ASAP (1994)
Andreas Ast, Jürgen Becker, Reiner W. Hartenstein, Rainer Kress, Helmut Reinig, Karin Schmidt
Data-Procedural Languages for FPL-based Machines. FPL (1994)
Rainer Kress, Elmar U. K. Melcher, Reiner W. Hartenstein, Michel Dana
CMOS interconnect modelling for timing analysis. Microprocess. Microprogramming 37 (1-5) (1993)
Andreas Ast, Reiner W. Hartenstein, Rainer Kress, Helmut Reinig, Karin Schmidt
Novel High Performance Machine Paradigms and Fast- Turnaround ASIC Design Methods. FPL (1992)

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Publication Activity (10 Years)

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Rainer Kress