Helmut Reinig

Publication Activity (10 Years)

Years Active: 1992-2014
Publications (10 Years): 0

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DATE

CODES+ISSS

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Kaiserslautern University of Technology, Germany (PHD)

Education History

Kaiserslautern University of Technology, Germany

PHD

Publications

Vladimir Todorov, Daniel Mueller-Gritschneder, Helmut Reinig, Ulf Schlichtmann
Deterministic Synthesis of Hybrid Application-Specific Network-on-Chip Topologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (10) (2014)
Vladimir Todorov, Daniel Mueller-Gritschneder, Helmut Reinig, Ulf Schlichtmann
A spectral clustering approach to application-specific network-on-chip synthesis. DATE (2013)
Vladimir Todorov, Daniel Mueller-Gritschneder, Helmut Reinig, Ulf Schlichtmann
Automated construction of a cycle-approximate transaction level model of a memory controller. DATE (2012)
Vladimir Todorov, Alberto Ghiribaldi, Helmut Reinig, Davide Bertozzi, Ulf Schlichtmann
Non-intrusive trace & debug noc architecture with accurate timestamping for GALS SoCs. CODES+ISSS (2012)
Hervé Tatenguem, Daniele Ludovici, Alessandro Strano, Davide Bertozzi, Helmut Reinig
Contrasting multi-synchronous MPSoC design styles for fine-grained clock domain partitioning: the full-HD video playback case study. NoCArc@MICRO (2011)
Andreas Lankes, Thomas Wild, Andreas Herkersdorf, Sören Sonntag, Helmut Reinig
Comparison of Deadlock Recovery and Avoidance Mechanisms to Approach Message Dependent Deadlocks in On-chip Networks. NOCS (2010)
Andreas Lankes, Andreas Herkersdorf, Sören Sonntag, Helmut Reinig
NoC topology exploration for mobile multimedia applications. ICECS (2009)
Sören Sonntag, Helmut Reinig
An Efficient Weighted-Round-Robin Algorithm for Multiprocessor Architectures. Annual Simulation Symposium (2008)
Markus Brandstetter, Torsten Harms, Helmut Reinig, Michael Vanrompay
Codevelopment of long haul ISDN transceiver and design methodology improves time to market. ICECS (1998)
Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig
High-performance computing using a reconfigurable accelerator. Concurr. Pract. Exp. 8 (6) (1996)
Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig
CoDe-C: A Novel Two-Level Hardware/Software Co-Design Framework. VLSI Design (1996)
Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig, Karin Schmidt
A Parallelizing Compilation Method for the Map-oriented Machine. ASAP (1995)
Reiner W. Hartenstein, Rainer Kress, Helmut Reinig
A New FPGA Architecture for Word-Oriented Datapaths. FPL (1994)
Reiner W. Hartenstein, Rainer Kress, Helmut Reinig
A dynamically reconfigurable wavefront array architecture for evaluation of expressions. ASAP (1994)
Andreas Ast, Jürgen Becker, Reiner W. Hartenstein, Rainer Kress, Helmut Reinig, Karin Schmidt
Data-Procedural Languages for FPL-based Machines. FPL (1994)
Andreas Ast, Reiner W. Hartenstein, Rainer Kress, Helmut Reinig, Karin Schmidt
Novel High Performance Machine Paradigms and Fast- Turnaround ASIC Design Methods. FPL (1992)

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Publication Activity (10 Years)

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Helmut Reinig