Heinrich Meyr

Publication Activity (10 Years)

Years Active: 1975-2020
Publications (10 Years): 4

Top Venues

CoRR

IEEE Trans. Inf. Theory

PIMRC

ICRA

Publications

Peng Huang, Heinrich Meyr, Meik Dörpinghaus, Gerhard P. Fettweis
Observability Analysis of Flight State Estimation for UAVs and Experimental Validation. ICRA (2020)
Meik Dörpinghaus, Izaak Neri, Édgar Roldán, Heinrich Meyr, Frank Jülicher
Testing Optimality of Sequential Decision-Making. CoRR (2018)
Dan Zhang, Heinrich Meyr
On the Performance Gap Between ML and Iterative Decoding of Finite-Length Turbo-Coded BICM in MIMO Systems. IEEE Trans. Commun. 65 (8) (2017)
Meik Dorpinghaus, Édgar Roldán, Izaak Neri, Heinrich Meyr, Frank Jülicher
An information theoretic analysis of sequential decision-making. ISIT (2017)
Meik Dörpinghaus, Édgar Roldán, Izaak Neri, Heinrich Meyr, Frank Jülicher
An Information Theoretic Analysis of Sequential Decision-Making. CoRR (2015)
I-Wei Lai, Chia-Han Lee, Gerd Ascheid, Heinrich Meyr, Tzi-Dar Chiueh
Channel-aware local search (CA-LS) for iterative MIMO detection. PIMRC (2015)
Meik Dörpinghaus, Günther Koliander, Giuseppe Durisi, Erwin Riegler, Heinrich Meyr
Oversampling Increases the Pre-Log of Noncoherent Fading Channels. CoRR (2014)
Meik Dörpinghaus, Günther Koliander, Giuseppe Durisi, Erwin Riegler, Heinrich Meyr
Oversampling Increases the Pre-Log of Noncoherent Rayleigh Fading Channels. IEEE Trans. Inf. Theory 60 (9) (2014)
Meik Dorpinghaus, Heinrich Meyr, Rudolf Mathar
On the Achievable Rate of Stationary Rayleigh Flat-Fading Channels With Gaussian Inputs. IEEE Trans. Inf. Theory 59 (4) (2013)
Meik Dorpinghaus, Adrian Ispas, Heinrich Meyr
On the Gain of Joint Processing of Pilot and Data Symbols in Stationary Rayleigh Fading Channels. IEEE Trans. Inf. Theory 58 (5) (2012)
Filippo Borlenghi, Ernst Martin Witte, Gerd Ascheid, Heinrich Meyr, Andreas Burg
65 nm CMOS gigabit MIMO iterative detection and decoding receiver. ESSCIRC (2012)
Filippo Borlenghi, Dominik Auras, Ernst Martin Witte, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
An FPGA-accelerated testbed for hardware component development in MIMO wireless communication systems. ICSAMOS (2012)
Cristina Silvano, William Fornaciari, Stefano Crespi-Reghizzi, Giovanni Agosta, Gianluca Palermo, Vittorio Zaccaria, Patrick Bellasi, Fabrizio Castro, Simone Corbetta, Ettore Speziale, Diego Melpignano, J. M. Zins, David Siorpaes, Heiko Hübert, Benno Stabernack, Jens Brandenburg, Martin Palkovic, Praveen Raghavan, Chantal Ykman-Couvreur, Alexandros Bartzas, Dimitrios Soudris, Torsten Kempf, Gerd Ascheid, Heinrich Meyr, Junaid Ansari, Petri Mähönen, Bart Vanthournout
Parallel paradigms and run-time management techniques for many-core architectures: the 2PARMA approach. INA-OCMC@HiPEAC (2012)
Dan Zhang, Gaojian Wang, Gerd Ascheid, Heinrich Meyr
Searching for optimal scheduling of MIMO doubly iterative receivers: An ant colony optimization-based method. GLOBECOM (2012)
I-Wei Lai, Chien-Yi Wang, Tzi-Dar Chiueh, Gerd Ascheid, Heinrich Meyr
Asymptotic Coded BER Analysis for MIMO BICM-ID with Quantized Extrinsic LLR. IEEE Trans. Commun. 60 (10) (2012)
I-Wei Lai, Gerd Ascheid, Heinrich Meyr, Tzi-Dar Chiueh
Efficient Channel-Adaptive MIMO Detection Using Just-Acceptable Error Rate. IEEE Trans. Wirel. Commun. 10 (1) (2011)
Filippo Borlenghi, Ernst Martin Witte, Gerd Ascheid, Heinrich Meyr, Andreas Peter Burg
A 772Mbit/s 8.81bit/nJ 90nm CMOS soft-input soft-output sphere decoder. A-SSCC (2011)
Meik Dörpinghaus, Heinrich Meyr
On the Achievable Rate of Stationary Rayleigh Flat-Fading Channels with Gaussian Inputs CoRR (2011)
Hanno Scharwächter, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
A retargetable framework for compiler/architecture co-development. Des. Autom. Embed. Syst. 15 (3-4) (2011)
Meik Dörpinghaus, Adrian Ispas, Heinrich Meyr
On the Gain of Joint Processing of Pilot and Data Symbols in Stationary Rayleigh Fading Channels CoRR (2011)
Meik Dorpinghaus, Adrian Ispas, Heinrich Meyr
Achievable rate with receivers using iterative channel estimation in stationary fading channels. ISWCS (2011)
Frank Kienle, Norbert Wehn, Heinrich Meyr
On Complexity, Energy- and Implementation-Efficiency of Channel Decoders. IEEE Trans. Commun. 59 (12) (2011)
I-Wei Lai, Gerd Ascheid, Heinrich Meyr, Tzi-Dar Chiueh
Asymptotic BER Analysis for MIMO-BICM with MMSE Detection and Channel Estimation. ICC (2011)
Cristina Silvano, William Fornaciari, Stefano Crespi-Reghizzi, Giovanni Agosta, Gianluca Palermo, Vittorio Zaccaria, Patrick Bellasi, Fabrizio Castro, Simone Corbetta, Andrea Di Biagio, Ettore Speziale, Michele Tartara, Diego Melpignano, J. M. Zins, David Siorpaes, Heiko Hübert, Benno Stabernack, Jens Brandenburg, Martin Palkovic, Praveen Raghavan, Chantal Ykman-Couvreur, Alexandros Bartzas, Sotirios Xydis, Dimitrios Soudris, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Junaid Ansari, Petri Mähönen, Bart Vanthournout
2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-Core Architectures. ISVLSI (Selected papers) (2010)
Cristina Silvano, William Fornaciari, Stefano Crespi-Reghizzi, Giovanni Agosta, Gianluca Palermo, Vittorio Zaccaria, Patrick Bellasi, Fabrizio Castro, Simone Corbetta, Andrea Di Biagio, Ettore Speziale, Michele Tartara, David Siorpaes, Heiko Hübert, Benno Stabernack, Jens Brandenburg, Martin Palkovic, Praveen Raghavan, Chantal Ykman-Couvreur, Alexandros Bartzas, Sotirios Xydis, Dimitrios Soudris, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Junaid Ansari, Petri Mähönen, Bart Vanthournout
2PARMA: Parallel Paradigms and Run-Time Management Techniques for Many-Core Architectures. ISVLSI (2010)
David Kammler, Ernst Martin Witte, Anupam Chattopadhyay, Bastian Bauwens, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
Automatic Generation of Memory Interfaces for ASIPs. Int. J. Embed. Real Time Commun. Syst. 1 (3) (2010)
Lars Schmitt, Heinrich Meyr
A Systematic Framework for Iterative Maximum Likelihood Receiver Design. IEEE Trans. Commun. 58 (7) (2010)
Jerónimo Castrillón, Ricardo Velasquez, Anastasia Stulova, Weihua Sheng, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
Trace-based KPN composability analysis for mapping simultaneous applications to MPSoC platforms. DATE (2010)
Lars Schmitt, Heinrich Meyr, Dan Zhang
Systematic Design of Iterative ML Receivers for Flat Fading Channels. IEEE Trans. Commun. 58 (7) (2010)
Torsten Kempf, Stefan Wallentowitz, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
Analytical and Simulation-based Design Space Exploration of Software Defined Radios. Int. J. Parallel Program. 38 (3-4) (2010)
Ernst Martin Witte, Filippo Borlenghi, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
A Scalable VLSI Architecture for Soft-Input Soft-Output Single Tree-Search Sphere Decoding. IEEE Trans. Circuits Syst. II Express Briefs (9) (2010)
Dan Zhang, Konstantinos Nikitopoulos, I-Wei Lai, Gerd Ascheid, Heinrich Meyr
Iterative channel estimation control for MIMO-OFDM Systems. CISS (2010)
Chien-Yi Wang, I-Wei Lai, Tzi-Dar Chiueh, Gerd Ascheid, Heinrich Meyr
BER analysis for MIMO BICM-ID assuming finite precision of extrinsic LLR. ISITA (2010)
Frank Kienle, Norbert Wehn, Heinrich Meyr
On Complexity, Energy- and Implementation-Efficiency of Channel Decoders CoRR (2010)
Meik Dorpinghaus, Heinrich Meyr, Gerd Ascheid
The achievable rate of stationary rayleigh flat-fading channels with IID input symbols. ISITA (2010)
Lei Gao, Jia Huang, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
TotalProf: a fast and accurate retargetable source code profiler. CODES+ISSS (2009)
David Kammler, Bastian Bauwens, Ernst Martin Witte, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Anupam Chattopadhyay
Automatic generation of memory interfaces. SoC (2009)
Venkatesh Ramakrishnan, Joschka zur Jacobsmuehlen, I-Wei Lai, Torsten Kempf, Marc Adrat, Gerd Ascheid, Markus Antweiler, Heinrich Meyr
Efficient implementations from libraries: Analyzing the influence of configuration parameters on key performance properties. PIMRC (2009)
Jianjiang Ceng, Weihua Sheng, Jerónimo Castrillón, Anastasia Stulova, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
A high-level virtual platform for early MPSoC software development. CODES+ISSS (2009)
Ernst Martin Witte, Filippo Borlenghi, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
A Scalable VLSI Architecture for Soft-Input Soft-Output Depth-First Sphere Decoding CoRR (2009)
David Kammler, Junqing Guan, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
A Fast and Flexible Platform for Fault Injection and Evaluation in Verilog-Based Simulations. SSIRI (2009)
Manuel Hohenauer, Felix Engel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
A SIMD optimization framework for retargetable compilers. ACM Trans. Archit. Code Optim. 6 (1) (2009)
Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs). SAMOS (2009)
Torsten Kempf, Stefan Wallentowitz, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
A Workbench for Analytical and Simulation Based Design Space Exploration of Software Defined Radios. VLSI Design (2009)
David Kammler, Diandian Zhang, Peter Schwabe, Hanno Scharwächter, Markus Langenberg, Dominik Auras, Gerd Ascheid, Rainer Leupers, Rudolf Mathar, Heinrich Meyr
Designing an ASIP for Cryptographic Pairings over Barreto-Naehrig Curves. IACR Cryptol. ePrint Arch. 2009 (2009)
I-Wei Lai, Chun-Hao Liao, Ernst Martin Witte, David Kammler, Filippo Borlenghi, Konstantinos Nikitopoulos, Venkatesh Ramakrishnan, Dan Zhang, Tzi-Dar Chiueh, Gerd Ascheid, Heinrich Meyr
Searching in the Delta Lattice: An Efficient MIMO Detection for Iterative Receivers. GLOBECOM (2009)
I-Wei Lai, Gerd Ascheid, Heinrich Meyr, Tzi-Dar Chiueh
Low-Complexity Channel-Adaptive MIMO Detection with Just-Acceptable Error Rate. VTC Spring (2009)
Anupam Chattopadhyay, Arnab Sinha, Diandian Zhang, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
Integrated verification approach during ADL-driven processor design. Microelectron. J. 40 (7) (2009)
Chun-Hao Liao, I-Wei Lai, Konstantinos Nikitopoulos, Filippo Borlenghi, David Kammler, Ernst Martin Witte, Dan Zhang, Tzi-Dar Chiueh, Gerd Ascheid, Heinrich Meyr
Combining orthogonalized partial metrics: Efficient enumeration for soft-input sphere decoder. PIMRC (2009)
Venkatesh Ramakrishnan, Ernst Martin Witte, Torsten Kempf, David Kammler, Gerd Ascheid, Heinrich Meyr, Marc Adrat, Markus Antweiler
Efficient And Portable SDR Waveform Development: The Nucleus Concept CoRR (2009)
Manuel Hohenauer, Felix Engel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gerrit Bette, Balpreet Singh
Retargetable Code Optimization for Predicated Execution. DATE (2008)
Meik Dörpinghaus, Gerd Ascheid, Heinrich Meyr, Rudolf Mathar
Optimal PSK signaling over stationary Rayleigh fading channels. ISIT (2008)
Anupam Chattopadhyay, Harold Ishebabi, Xiaolin Chen, Zoltan Endre Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors. ACM Trans. Embed. Comput. Syst. 7 (4) (2008)
Tim Kogel, Malte Doerper, Torsten Kempf, Andreas Wieferink, Rainer Leupers, Heinrich Meyr
Virtual architecture mapping: a SystemC based methodology for architectural exploration of System-on-Chips. Int. J. Embed. Syst. 3 (3) (2008)
Lei Gao, Kingshuk Karuri, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
Multiprocessor performance estimation using hybrid simulation. DAC (2008)
Susanne Godtmann, I-Wei Lai, Gerd Ascheid, Tzi-Dar Chiueh, Heinrich Meyr
Tight Approximation of the Bit Error Rate for BICM(-ID) Assuming Imperfect CSI. IEEE Trans. Wirel. Commun. 7 (11-2) (2008)
Markus Jordan, Martin Senst, Gerd Ascheid, Heinrich Meyr
Long-Term Beamforming in Single Frequency Networks using Semidefinite Relaxation. VTC Spring (2008)
Andreas Wieferink, Tim Kogel, Olaf Zerres, Rainer Leupers, Heinrich Meyr
SoC multiprocessor debugging and synchronisation using generic dynamic-connect debugger frontends. Int. J. Embed. Syst. 3 (3) (2008)
Diandian Zhang, Anupam Chattopadhyay, David Kammler, Ernst Martin Witte, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
Power-efficient Instruction Encoding Optimization for Various Architecture Classes. J. Comput. 3 (3) (2008)
Jianjiang Ceng, Jerónimo Castrillón, Weihua Sheng, Hanno Scharwächter, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tsuyoshi Isshiki, Hiroaki Kunieda
MAPS: an integrated framework for MPSoC application parallelization. DAC (2008)
I-Wei Lai, Susanne Godtmann, Tzi-Dar Chiueh, Gerd Ascheid, Heinrich Meyr
Asymptotic BER Analysis for MIMO-BICM with Zero-Forcing Detectors Assuming Imperfect CSI. ICC (2008)
Anupam Chattopadhyay, Xiaolin Chen, Harold Ishebabi, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
High-level Modelling and Exploration of Coarse-grained Re-configurable Architectures. DATE (2008)
Kingshuk Karuri, Anupam Chattopadhyay, Xiaolin Chen, David Kammler, Ling Hao, Rainer Leupers, Heinrich Meyr, Gerd Ascheid
A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors. IEEE Trans. Very Large Scale Integr. Syst. 16 (10) (2008)
Martin Senst, Markus Jordan, Meik Dorpinghaus, Michael Farber, Gerd Ascheid, Heinrich Meyr
Joint Reduction of Peak-to-Average Power Ratio and Out-of-Band Power in OFDM Systems. GLOBECOM (2007)
Stefan Kraemer, Lei Gao, Jan Weinstock, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
HySim: a fast simulation framework for embedded software development. CODES+ISSS (2007)
Hanno Scharwächter, David Kammler, Andreas Wieferink, Manuel Hohenauer, Kingshuk Karuri, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
ASIP architecture exploration for efficient IPSec encryption: A case study. ACM Trans. Embed. Comput. Syst. 6 (2) (2007)
Lei Gao, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
A fast and generic hybrid simulation approach using C virtual machine. CASES (2007)
Markus Jordan, Lars Schmitt, Gerd Ascheid, Heinrich Meyr
Prediction of Downlink SNR for Opportunistic Beamforming. WCNC (2007)
Markus Jordan, Gerd Ascheid, Heinrich Meyr
Performance Evaluation of Opportunistic Beamforming with SINR Prediction for HSDPA. VTC Spring (2007)
Anupam Chattopadhyay, W. Ahmed, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
Design space exploration of partially re-configurable embedded processors. DATE (2007)
Anupam Chattopadhyay, Zoltan Endre Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
Pre- and Post-Fabrication Architecture Exploration for Partially Reconfigurable VLIW Processors. IEEE International Workshop on Rapid System Prototyping (2007)
Hanno Scharwächter, Jonghee M. Youn, Rainer Leupers, Yunheung Paek, Gerd Ascheid, Heinrich Meyr
A code-generator generator for multi-output instructions. CODES+ISSS (2007)
Kingshuk Karuri, Anupam Chattopadhyay, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
Increasing data-bandwidth to instruction-set extensions through register clustering. ICCAD (2007)
Susanne Godtmann, André Pollok, Niels Hadaschik, Gerd Ascheid, Heinrich Meyr
On the Influence of Pilot Symbol and Data Symbol Positioning on Turbo Synchronization. VTC Spring (2007)
Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
Interactive presentation: SoftSIMD - exploiting subword parallelism using source code transformations. DATE (2007)
Hanno Scharwächter, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
An interprocedural code optimization technique for network processors using hardware multi-threading support. DATE (2006)
Torsten Kempf, Kingshuk Karuri, Stefan Wallentowitz, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
A SW performance estimation framework for early system-level-design using fine-grained instrumentation. DATE (2006)
Niels Hadaschik, Gerd Ascheid, Heinrich Meyr
Achievable Data Rate of Wideband OFDM With Data-Aided Channel Estimation. PIMRC (2006)
Meik Dörpinghaus, Lars Schmitt, Ingo Viering, Axel Klein, Joachim Schmid, Gerd Ascheid, Heinrich Meyr
Enhanced Predictive Up/Down Power Control for CDMA Systems. ICC (2006)
Anupam Chattopadhyay, B. Geukes, David Kammler, Ernst Martin Witte, Oliver Schliebusch, Harold Ishebabi, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
Automatic ADL-based operand isolation for embedded processors. DATE (2006)
Manuel Hohenauer, Christoph Schumacher, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Hans van Someren
Retargetable code optimization with SIMD instructions. CODES+ISSS (2006)
Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Monu Kedia
Design and implementation of a modular and portable IEEE 754 compliant floating-point unit. DATE Designers' Forum (2006)
Peter Wintermayr, Reiner W. Hartenstein, Heinrich Meyr, Steve Leibson
Flexibility and low power: a contradiction in terms? ISLPED (2006)
Anupam Chattopadhyay, Arnab Sinha, Diandian Zhang, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
Integrated Verification Approach during ADL-Driven Processor Design. IEEE International Workshop on Rapid System Prototyping (2006)
Kingshuk Karuri, Christian Huben, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
Memory Access Micro-Profiling for ASIP Design. DELTA (2006)
Luca Fanucci, Michele Cassiano, Sergio Saponara, David Kammler, Ernst Martin Witte, Oliver Schliebusch, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
ASIP design and synthesis for non linear filtering in image processing. DATE Designers' Forum (2006)
Harold Ishebabi, Gerd Ascheid, Heinrich Meyr, Oguzhan Atak, Abdullah Atalar, Erdal Arikan
An efficient parallelization technique for high throughput FFT-ASIPs. ISCAS (2006)
Jianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun
Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting. J. VLSI Signal Process. 43 (2-3) (2006)
Oguzhan Atak, Abdullah Atalar, Erdal Arikan, Harold Ishebabi, David Kammler, Gerd Ascheid, Heinrich Meyr, Mario Nicola, Guido Masera
Design of Application Specific Processors for the Cached FFT Algorithm. ICASSP (3) (2006)
Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tom Michiels, Achim Nohl, Tim Kogel
Retargetable generation of TLM bus interfaces for MP-SoC platforms. CODES+ISSS (2005)
Jianjiang Ceng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun
C Compiler Retargeting Based on Instruction Semantics Models. DATE (2005)
Oliver Schliebusch, Anupam Chattopadhyay, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Tim Kogel
A framework for automated and optimized ASIP implementation supporting multiple hardware description languages. ASP-DAC (2005)
Niels Hadaschik, Meik Dörpinghaus, Andreas Senst, Ole Harmjanz, Uwe Käufer, Gerd Ascheid, Heinrich Meyr
Improving MIMO phase noise estimation by exploiting spatial correlations. ICASSP (3) (2005)
Torsten Kempf, Malte Doerper, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tim Kogel, Bart Vanthournout
A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms. DATE (2005)
Oliver Schliebusch, Anupam Chattopadhyay, Ernst Martin Witte, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
Optimization Techniques for ADL-Driven RTL Processor Synthesis. IEEE International Workshop on Rapid System Prototyping (2005)
Kingshuk Karuri, Mohammad Abdullah Al Faruque, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
Fine-grained application source code profiling for ASIP design. DAC (2005)
Mohammad Mostafizur Rahman Mozumdar, Kingshuk Karuri, Anupam Chattopadhyay, Stefan Kraemer, Hanno Scharwächter, Heinrich Meyr, Gerd Ascheid, Rainer Leupers
Instruction Set Customization of Application Specific Processors for Network Processing: A Case Study. ASAP (2005)
Manuel Hohenauer, Hanno Scharwächter, Kingshuk Karuri, Oliver Wahlen, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Hans van Someren
A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models. DATE (2004)
Gunnar Braun, Achim Nohl, Andreas Hoffmann, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr
A universal technique for fast and flexible instruction-set architecture simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (12) (2004)
Andreas Wieferink, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Achim Nohl
A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platform. DATE (2004)

Heinrich Meyr.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Heinrich Meyr