Benno Stabernack

Publication Activity (10 Years)

Years Active: 1999-2024
Publications (10 Years): 20

Top Topics

Fpga Implementation

High Throughput

Pipelined Architecture

Top Venues

IEEE Trans. Consumer Electron.

Publications

Philipp Kreowsky, Justin Knapheide, Benno Stabernack
An Approach Towards Distributed DNN Training on FPGA Clusters. ARCS (2024)
Philipp Kreowsky, Justin Knapheide, Benno Stabernack
Challenges Using FPGA Clusters for Distributed CNN Training. FPL (2023)
Justin Knapheide, Philipp Kreowsky, Benno Stabernack
Demonstrating NADA: A Workflow for Distributed CNN Training on FPGA Clusters. FPL (2023)
Niklas Schelten, Fritjof Steinert, Justin Knapheide, Anton Schulte, Benno Stabernack
A High-Throughput, Resource-Efficient Implementation of the RoCEv2 Remote DMA Protocol and its Application. ACM Trans. Reconfigurable Technol. Syst. 16 (1) (2023)
Fritjof Steinert, Benno Stabernack
FPGA-Based Network-Attached Accelerators - An Environmental Life Cycle Perspective. ARCS (2023)
Steffen Christgau, Dylan Everingham, Florian Mikolajczak, Niklas Schelten, Bettina Schnor, Max Schrötter, Benno Stabernack, Fritjof Steinert
Enabling Communication with FPGA-based Network-attached Accelerators for HPC Workloads. SC Workshops (2023)
Michal Stec, Benno Stabernack, Clemens Kubach
Towards an optimal right-turn assistant system to avoid accidents with vulnerable traffic participants. MECO (2022)
Viktor Herrmann, Justin Knapheide, Fritjof Steinert, Benno Stabernack
A YOLO v3-tiny FPGA Architecture using a Reconfigurable Hardware Accelerator for Real-time Region of Interest Detection. DSD (2022)
Fritjof Steinert, Benno Stabernack
Architecture of a Low Latency H.264/AVC Video Codec for Robust ML based Image Classification. J. Signal Process. Syst. 94 (7) (2022)
Benno Stabernack, Fritjof Steinert
Architecture of a Low Latency H.264/AVC Video Codec for robust ML based Image Classification. DASIP (2021)
Fritjof Steinert, Justin Knapheide, Benno Stabernack
Demonstration of a Distributed Accelerator Framework for Energy-efficient ML Processing. FPL (2021)
Philipp Kreowsky, Benno Stabernack
A Full-Featured FPGA-Based Pipelined Architecture for SIFT Extraction. IEEE Access 9 (2021)
Niklas Schelten, Fritjof Steinert, Anton Schulte, Benno Stabernack
A High-Throughput, Resource-Efficient Implementation of the RoCEv2 Remote DMA Protocol for Network-Attached Hardware Accelerators. FPT (2020)
Fritjof Steinert, Philipp Kreowsky, Eric L. Wisotzky, Christian Unger, Benno Stabernack
A Hardware/Software Framework for the Integration of FPGA-based Accelerators into Cloud Computing Infrastructures. SmartCloud (2020)
Fritjof Steinert, Niklas Schelten, Anton Schulte, Benno Stabernack
Hardware and Software Components towards the Integration of Network-Attached Accelerators into Data Centers. DSD (2020)
Justin Knapheide, Benno Stabernack, Maximilian Kuhnke
A High Throughput MobileNetV2 FPGA Implementation Based on a Flexible Architecture for Depthwise Separable Convolution. FPL (2020)
Michal Stec, Viktor Herrmann, Benno Stabernack
Using Time-of-Flight Sensors for People Counting Applications. DASIP (2019)
Michal Stec, Viktor Herrmann, Benno Stabernack
Multi-Sensor-Fusion System for People Counting Applications. SA (2019)
Christian Herglotz, Dominic Springer, Marc Reichenbach, Benno Stabernack, André Kaup
Modeling the Energy Consumption of the HEVC Decoding Process. IEEE Trans. Circuits Syst. Video Technol. 28 (1) (2018)
Jens Brandenburg, Benno Stabernack
Simulation-based HW/SW co-exploration of the concurrent execution of HEVC intra encoding algorithms for heterogeneous multi-core architectures. J. Syst. Archit. 77 (2017)
Benno Stabernack, Jan Moller, Jan Hahlbeck, Jens Brandenburg
Demonstrating an FPGA implementation of a full HD real-time HEVC decoder with memory optimizations for range extensions support. DASIP (2015)
Jens Brandenburg, Benno Stabernack
Exploring the concurrent execution of HEVC intra encoding algorithms for heterogeneous multi core architectures. DASIP (2015)
Denis Engelhardt, Jan Moller, Jan Hahlbeck, Benno Stabernack
FPGA implementation of a full HD real-time HEVC main profile decoder. IEEE Trans. Consumer Electron. 60 (3) (2014)
Henryk Richter, Benno Stabernack, Volker Kühn
Architectural Decomposition of Video Decoders by Meansof an Intermediate Data Stream Format. J. Signal Process. Syst. 75 (1) (2014)
Jan Hahlbeck, Benno Stabernack
A 4k capable FPGA based high throughput binary arithmetic decoder for H.265/MPEG-HEVC. ICCE-Berlin (2014)
Martin Werner, Benno Stabernack, Christian Riechert
Hardware implementation of a full HD real-time disparity estimation algorithm. IEEE Trans. Consumer Electron. 60 (1) (2014)
Jens Brandenburg, Benno Stabernack
Memory access analysis and optimization of a parallel H.264/SVC decoder for an embedded multi-core platform. DASIP (2013)
Heiko Hübert, Benno Stabernack, Frederik Zilly
Architecture of a Low Latency Image Rectification Engine for Stereoscopic 3-D HDTV Processing. IEEE Trans. Circuits Syst. Video Technol. 23 (5) (2013)
Jens Brandenburg, Benno Stabernack
A Generic and Non-intrusive Profiling Methodology for SystemC Multi-core Platform Simulation Models. ARCS (2012)
Henryk Richter, Benno Stabernack, Volker Kühn
Architectural decomposition of video decoders for many core architectures. DASIP (2012)
Cristina Silvano, William Fornaciari, Stefano Crespi-Reghizzi, Giovanni Agosta, Gianluca Palermo, Vittorio Zaccaria, Patrick Bellasi, Fabrizio Castro, Simone Corbetta, Ettore Speziale, Diego Melpignano, J. M. Zins, David Siorpaes, Heiko Hübert, Benno Stabernack, Jens Brandenburg, Martin Palkovic, Praveen Raghavan, Chantal Ykman-Couvreur, Alexandros Bartzas, Dimitrios Soudris, Torsten Kempf, Gerd Ascheid, Heinrich Meyr, Junaid Ansari, Petri Mähönen, Bart Vanthournout
Parallel paradigms and run-time management techniques for many-core architectures: the 2PARMA approach. INA-OCMC@HiPEAC (2012)
Cristina Silvano, William Fornaciari, Stefano Crespi-Reghizzi, Giovanni Agosta, Gianluca Palermo, Vittorio Zaccaria, Patrick Bellasi, Fabrizio Castro, Simone Corbetta, Ettore Speziale, Diego Melpignano, J. M. Zins, Heiko Hübert, Benno Stabernack, Jens Brandenburg, Martin Palkovic, Praveen Raghavan, Chantal Ykman-Couvreur, Iraklis Anagnostopoulos, Alexandros Bartzas, Dimitrios Soudris, Torsten Kempf, Gerd Ascheid, Junaid Ansari, Petri Mähönen, Bart Vanthournout
Invited paper: Parallel programming and run-time resource management framework for many-core platforms: The 2PARMA approach. ReCoSoC (2011)
Cristina Silvano, William Fornaciari, Stefano Crespi-Reghizzi, Giovanni Agosta, Gianluca Palermo, Vittorio Zaccaria, Patrick Bellasi, Fabrizio Castro, Simone Corbetta, Andrea Di Biagio, Ettore Speziale, Michele Tartara, Diego Melpignano, J. M. Zins, David Siorpaes, Heiko Hübert, Benno Stabernack, Jens Brandenburg, Martin Palkovic, Praveen Raghavan, Chantal Ykman-Couvreur, Alexandros Bartzas, Sotirios Xydis, Dimitrios Soudris, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Junaid Ansari, Petri Mähönen, Bart Vanthournout
2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-Core Architectures. ISVLSI (Selected papers) (2010)
Cristina Silvano, William Fornaciari, Stefano Crespi-Reghizzi, Giovanni Agosta, Gianluca Palermo, Vittorio Zaccaria, Patrick Bellasi, Fabrizio Castro, Simone Corbetta, Andrea Di Biagio, Ettore Speziale, Michele Tartara, David Siorpaes, Heiko Hübert, Benno Stabernack, Jens Brandenburg, Martin Palkovic, Praveen Raghavan, Chantal Ykman-Couvreur, Alexandros Bartzas, Sotirios Xydis, Dimitrios Soudris, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Junaid Ansari, Petri Mähönen, Bart Vanthournout
2PARMA: Parallel Paradigms and Run-Time Management Techniques for Many-Core Architectures. ISVLSI (2010)
Heiko Hübert, Benno Stabernack
Profiling-Based Hardware/Software Co-Exploration for the Design of Video Coding Architectures. IEEE Trans. Circuits Syst. Video Technol. 19 (11) (2009)
Heiko Hübert, Benno Stabernack
Power Modeling of an Embedded RISC Core for Function-Accurate Energy Profiling. MBMV (2009)
Henryk Richter, Benno Stabernack, Erika Müller
Generic algorithms for motion compensation and transformation. Real-Time Image Processing (2008)
Heiko Hübert, Benno Stabernack, Kai-Immo Wels
Performance and Memory Profiling for Embedded System Design. SIES (2007)
Benno Stabernack, Kai-Immo Wels, Heiko Hübert
A System on a Chip Architecture of an H.264/AVC Coprocessor for DVB-H and DMB Applications. IEEE Trans. Consumer Electron. 53 (4) (2007)
Heiko Hübert, Benno Stabernack, Henryk Richter
Tool-aided performance analysis and optimization of multimedia applications. ESTIMedia (2004)
Corina Scheiter, Rainer Steffen, Markus Zeller, Rudi Knorr, Benno Stabernack, Kai-Immo Wels
A system for QOS-enabled MPEG-4 video transmission over Bluetooth for mobile applications. ICME (2003)
Mladen Berekovic, Hans-Joachim Stolberg, Mark Bernd Kulaczewski, Peter Pirsch, Henning Möller, Holger Runge, Johannes Kneip, Benno Stabernack
Instruction Set Extensions for MPEG-4 Video. J. VLSI Signal Process. 23 (1) (1999)