A YOLO v3-tiny FPGA Architecture using a Reconfigurable Hardware Accelerator for Real-time Region of Interest Detection.
Viktor HerrmannJustin KnapheideFritjof SteinertBenno StabernackPublished in: DSD (2022)
Keyphrases
- reconfigurable hardware
- region of interest
- field programmable gate array
- low cost
- real time
- pipelined architecture
- hardware implementation
- fpga device
- fpga technology
- hardware software
- hardware architecture
- xilinx virtex
- medical images
- embedded systems
- parallel computing
- hardware design
- dedicated hardware
- mammogram images
- evolvable hardware
- computing systems
- hardware and software
- functional units
- image processing
- massively parallel
- processing elements
- image processing algorithms
- signal processing
- data acquisition
- computer vision