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Demonstrating an FPGA implementation of a full HD real-time HEVC decoder with memory optimizations for range extensions support.

Benno StabernackJan MollerJan HahlbeckJens Brandenburg
Published in: DASIP (2015)
Keyphrases
  • fpga implementation
  • hardware implementation
  • real time
  • field programmable gate array
  • low complexity
  • transfer function
  • high definition
  • neural network
  • scheduling problem
  • motion estimation