Oliver Schliebusch

Publication Activity (10 Years)

Years Active: 2001-2006
Publications (10 Years): 0

Publications

Anupam Chattopadhyay, B. Geukes, David Kammler, Ernst Martin Witte, Oliver Schliebusch, Harold Ishebabi, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
Automatic ADL-based operand isolation for embedded processors. DATE (2006)
Luca Fanucci, Michele Cassiano, Sergio Saponara, David Kammler, Ernst Martin Witte, Oliver Schliebusch, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
ASIP design and synthesis for non linear filtering in image processing. DATE Designers' Forum (2006)
Ernst Martin Witte, Anupam Chattopadhyay, Oliver Schliebusch, David Kammler
Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation. ICCD (2005)
Oliver Schliebusch, Anupam Chattopadhyay, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Tim Kogel
A framework for automated and optimized ASIP implementation supporting multiple hardware description languages. ASP-DAC (2005)
Oliver Schliebusch, Anupam Chattopadhyay, Ernst Martin Witte, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
Optimization Techniques for ADL-Driven RTL Processor Synthesis. IEEE International Workshop on Rapid System Prototyping (2005)
Gunnar Braun, Achim Nohl, Andreas Hoffmann, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr
A universal technique for fast and flexible instruction-set architecture simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (12) (2004)
Oliver Schliebusch, Anupam Chattopadhyay, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Mario Steinert, Gunnar Braun, Achim Nohl
RTL Processor Synthesis for Architecture Exploration and Implementation. DATE (2004)
Achim Nohl, Volker Greive, Gunnar Braun, Andreas Hoffmann, Rainer Leupers, Oliver Schliebusch, Heinrich Meyr
Instruction encoding synthesis for architecture exploration using hierarchical processor models. DAC (2003)
Gunnar Braun, Andreas Wieferink, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr, Achim Nohl
Processor/Memory Co-Exploration on Multiple Abstraction Levels. DATE (2003)
Achim Nohl, Gunnar Braun, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr, Andreas Hoffmann
A universal technique for fast and flexible instruction-set architecture simulation. DAC (2002)
Oliver Schliebusch, Andreas Hoffmann, Achim Nohl, Gunnar Braun, Heinrich Meyr
Architecture Implementation Using the Machine Description Language LISA. VLSI Design (2002)
Andreas Hoffmann, Tim Kogel, Achim Nohl, Gunnar Braun, Oliver Schliebusch, Oliver Wahlen, Andreas Wieferink, Heinrich Meyr
A novel methodology for the design of application-specificinstruction-set processors (ASIPs) using a machine description language. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20 (11) (2001)
Andreas Hoffmann, Oliver Schliebusch, Achim Nohl, Gunnar Braun, Oliver Wahlen, Heinrich Meyr
A Methodology for the Design of Application Specific Instruction Set Processors (ASIP) using the Machine Description Language LISA. ICCAD (2001)