Henrik Hulgaard

Publication Activity (10 Years)

Years Active: 1991-2003
Publications (10 Years): 0

Publications

Poul Frederick Williams, Henrik Reif Andersen, Henrik Hulgaard
Satisfiability checking using Boolean Expression Diagrams. Int. J. Softw. Tools Technol. Transf. 5 (1) (2003)
Henrik Reif Andersen, Henrik Hulgaard
Boolean Expression Diagrams. Inf. Comput. 179 (2) (2002)
Jesper B. Møller, Henrik Hulgaard, Henrik Reif Andersen
Symbolic model checking of timed guarded commands using difference decision diagrams. J. Log. Algebraic Methods Program. (2002)
Jesper B. Møller, Henrik Hulgaard, Henrik Reif Andersen
Timed Verification of Asynchronous Circuits. Concurrency and Hardware Design (2002)
Gerd Behrmann, Kim Guldstrand Larsen, Henrik Reif Andersen, Henrik Hulgaard, Jørn Lind-Nielsen
Verification of Hierarchical State/Event Systems using Reusability and Compositionality. Formal Methods Syst. Des. 21 (2) (2002)
Jørn Lind-Nielsen, Henrik Reif Andersen, Henrik Hulgaard, Gerd Behrmann, Kåre J. Kristoffersen, Kim Guldstrand Larsen
Verification of Large State/Event Systems Using Compositionality and Dependency Analysis. Formal Methods Syst. Des. 18 (1) (2001)
Poul Frederick Williams, Henrik Reif Andersen, Henrik Hulgaard
Satisfiability Checking Using Boolean Expression Diagrams. TACAS (2001)
Jørgen Staunstrup, Henrik Reif Andersen, Henrik Hulgaard, Jørn Lind-Nielsen, Kim Guldstrand Larsen, Gerd Behrmann, Kåre J. Kristoffersen, Arne Skou, Henrik Leerberg, Niels Bo Theilgaard
Practical Verification of Embedded Software. Computer 33 (5) (2000)
Henrik Hulgaard, Tod Amon
Symbolic timing analysis of asynchronous systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19 (10) (2000)
Gerd Behrmann, Kim Guldstrand Larsen, Henrik Reif Andersen, Henrik Hulgaard, Jørn Lind-Nielsen
Verification of Hierarchical State/Event Systems Using Reusability and Compositionality. TACAS (1999)
Jesper B. Møller, Jakob Lichtenberg, Henrik Reif Andersen, Henrik Hulgaard
Difference Decision Diagrams. CSL (1999)
Henrik Hulgaard, Poul Frederick Williams, Henrik Reif Andersen
Equivalence checking of combinational circuits using Boolean expression diagrams. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (7) (1999)
Tod Amon, Henrik Hulgaard
Symbolic Time Separation of Events. ASYNC (1999)
Poul Frederick Williams, Henrik Hulgaard, Henrik Reif Andersen
Equivalence checking of hierarchical combinational circuits. ICECS (1999)
Jesper B. Møller, Jakob Lichtenberg, Henrik Reif Andersen, Henrik Hulgaard
Fully Symbolic Model Checking of Timed Systems using Difference Decision Diagrams. Electron. Notes Theor. Comput. Sci. 23 (2) (1999)
Jørn Lind-Nielsen, Henrik Reif Andersen, Gerd Behrmann, Henrik Hulgaard, Kåre J. Kristoffersen, Kim Guldstrand Larsen
Verification of Large State/Event Systems Using Compositionality and Dependency Analysis. TACAS (1998)
Fen Jin, Henrik Hulgaard, Eduard Cerny
Maximum Time Separation of Events in Cyclic Systems with Linear and Latest Timing Constraints. FMCAD (1998)
Henrik Reif Andersen, Henrik Hulgaard
Boolean Expression Diagrams (Extended Abstract). LICS (1997)
Henrik Hulgaard, Steven M. Burns
Bounded Delay Timing Analysis of a Class of CSP Programs. Formal Methods Syst. Des. 11 (3) (1997)
Henrik Hulgaard, Steven M. Burns, Gaetano Borriello
Testing asynchronous circuits: A survey. Integr. 19 (3) (1995)
Henrik Hulgaard, Steven M. Burns, Tod Amon, Gaetano Borriello
An Algorithm for Exact Bounds on the Time Separation of Events in Concurrent Systems. IEEE Trans. Computers 44 (11) (1995)
Henrik Hulgaard, Steven M. Burns
Efficient Timing Analysis of a Class of Petri Nets. CAV (1995)
Henrik Hulgaard, Steven M. Burns
Bounded delay timing analysis of a class of CSP programs with choice. ASYNC (1994)
Henrik Hulgaard, Steven M. Burns, Tod Amon, Gaetano Borriello
Practical applications of an efficient time separation of events algorithm. ICCAD (1993)
Tod Amon, Henrik Hulgaard, Steven M. Burns, Gaetano Borriello
An Algorithm for Exact Bounds on the Time Separation of Events in Concurrent Systems. ICCD (1993)
Henrik Hulgaard, Per H. Christensen, Jørgen Staunstrup
Synthesizing Delay Insensitive Circuits from Verified Programs. Research Directions in High-Level Parallel Programming Languages (1991)