Equivalence checking of hierarchical combinational circuits.

Poul Frederick Williams Henrik Hulgaard Henrik Reif Andersen

Published in: ICECS (1999)

Keyphrases

logic circuits
asynchronous circuits
hierarchical structure
high speed
coarse to fine
delay insensitive
real time
machine learning
image processing
low cost
hierarchical clustering
low power
hierarchical model
hierarchical classification
circuit design
logic synthesis