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SRAM cells with full-swing single-ended bit line sensing for on-chip cache.
Fatih Hamzaoglu
Yibin Ye
Ali Keshavarzi
Kevin Zhang
Siva G. Narendra
Shekhar Borkar
Mircea R. Stan
Vivek De
Published in:
IEEE Trans. Very Large Scale Integr. Syst. (2002)
Keyphrases
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random access memory
processor core
design considerations
low cost
memory access
dynamic random access memory
response time
high speed
operating system
low power
embedded dram
real time
flash memory
single chip
memory subsystem