Naran Sirisantana

Publication Activity (10 Years)

Years Active: 2000-2005
Publications (10 Years): 0

Publications

Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy
Synthesis of skewed logic circuits. ACM Trans. Design Autom. Electr. Syst. 10 (2) (2005)
Naran Sirisantana, Bipul Chandra Paul, Kaushik Roy
Enhancing Yield at the End of the Technology Roadmap. IEEE Des. Test Comput. 21 (6) (2004)
Naran Sirisantana, Kaushik Roy
Low-Power Design Using Multiple Channel Lengths and Oxide Thicknesses. IEEE Des. Test Comput. 21 (1) (2004)
Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy
Integer linear programming-based synthesis of skewed logic circuits. ASP-DAC (2003)
Naran Sirisantana, Kaushik Roy
Selectively Clocked CMOS Logic Style for Low-Power Noise-Immune Operations in Scaled Technologies. DATE (2003)
Naran Sirisantana, Kaushik Roy
A time borrowing selectively clocked skewed logic for high-performance circuits in scaled technologies. ESSCIRC (2003)
Alexandre Solomatnikov, Dinesh Somasekhar, Naran Sirisantana, Kaushik Roy
Skewed CMOS: noise-tolerant high-performance low-power static circuit family. IEEE Trans. Very Large Scale Integr. Syst. 10 (4) (2002)
Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy
Synthesis of Selectively Clocked Skewed Logic Circuits. ISQED (2002)
Naran Sirisantana, Aiqun Cao, Shawn Davidson, Cheng-Kok Koh, Kaushik Roy
Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications. ISLPED (2001)
Naran Sirisantana, Liqiong Wei, Kaushik Roy
High-Performance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness. ICCD (2000)