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Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications.
Naran Sirisantana
Aiqun Cao
Shawn Davidson
Cheng-Kok Koh
Kaushik Roy
Published in:
ISLPED (2001)
Keyphrases
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low power
logic circuits
low cost
power consumption
high speed
delay insensitive
low power consumption
signal processor
single chip
gate array
vlsi circuits
high power
mixed signal
vlsi architecture
wireless transmission
asynchronous circuits
cmos technology