Selectively Clocked CMOS Logic Style for Low-Power Noise-Immune Operations in Scaled Technologies.
Naran SirisantanaKaushik RoyPublished in: DATE (2003)
Keyphrases
- low power
- power consumption
- logic circuits
- low cost
- high speed
- delay insensitive
- single chip
- cmos technology
- vlsi circuits
- energy dissipation
- digital signal processing
- high power
- vlsi architecture
- low power consumption
- wireless transmission
- wide dynamic range
- image sensor
- mixed signal
- signal to noise ratio
- noise model
- power reduction
- image processing
- ultra low power
- asynchronous circuits
- cmos image sensor
- hardware and software
- digital camera