Low-Power Design Using Multiple Channel Lengths and Oxide Thicknesses.

Naran Sirisantana Kaushik Roy

Published in: IEEE Des. Test Comput. (2004)

Keyphrases

low power
single chip
power consumption
low cost
low power consumption
high speed
vlsi architecture
wireless transmission
gate array
logic circuits
digital signal processing
power dissipation
power reduction
cmos technology
ultra low power
high power
mixed signal
vlsi circuits
computer simulation
cmos image sensor