A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management.
Yih WangUddalak BhattacharyaFatih HamzaogluPramod KolarYong-Gee NgLiqiong WeiYing ZhangKevin ZhangMark BohrPublished in: ISSCC (2009)
Keyphrases
- power consumption
- power management
- nm technology
- cmos technology
- clock gating
- low voltage
- low power
- power dissipation
- leakage current
- energy efficiency
- dynamic power management
- power reduction
- parallel processing
- energy saving
- circuit design
- design considerations
- field effect transistors
- response time
- high speed
- metal oxide