A 1.1 GHz 12 µA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications.
Yih WangHong Jo AhnUddalak BhattacharyaZhanping ChenTom CoanFatih HamzaogluWalid M. HafezChia-Hong JanPramod KolarSarvesh H. KulkarniJie-Feng LinYong-Gee NgIan PostLiqiong WeiYing ZhangKevin ZhangMark BohrPublished in: IEEE J. Solid State Circuits (2008)
Keyphrases
- cmos technology
- low power
- mobile applications
- power consumption
- ultra low power
- high speed
- low voltage
- low cost
- power dissipation
- leakage current
- power reduction
- user experience
- single chip
- parallel processing
- digital signal processing
- design process
- mixed signal
- image sensor
- mobile devices
- mobile phone
- design considerations
- low power consumption
- power management
- real time
- signal processing
- image processing