Jaydeep P. Kulkarni

Publication Activity (10 Years)

Years Active: 2004-2024
Publications (10 Years): 53

Top Topics

Schottky Barrier

Dynamic Random Access Memory

Boolean Satisfiability

Physical Design

Top Venues

IEEE J. Solid State Circuits

Publications

Yipeng Wang, Mengtian Yang, Chieh-Pu Lo, Jaydeep P. Kulkarni
30.6 Vecim: A 289.13GOPS/W RISC-V Vector Co-Processor with Compute-in-Memory Vector Register File for Efficient High-Performance Computing. ISSCC (2024)
Shanshan Xie, Can Ni, Aseem Sayal, Pulkit Jain, Fatih Hamzaoglu, Jaydeep P. Kulkarni
eDRAM-CIM: Reconfigurable Charge Domain Compute-In-Memory Design With Embedded Dynamic Random Access Memory Array Realizing Adaptive Data Converters. IEEE J. Solid State Circuits 59 (6) (2024)
Juhan Ahn, Saroj Satapathy, Jaydeep P. Kulkarni
Advancing Low-Voltage Complementary Reconfigurable Field-Effect Transistor Operation with Reduced Schottky Barriers. DRC (2024)
Mengtian Yang, Yipeng Wang, Shanshan Xie, Chieh-Pu Lo, Meizhi Wang, Sirish Oruganti, Rishabh Sehgal, Jaydeep P. Kulkarni
CILP: An Arbitrary-bit Precision All-digital Compute-in-memory Solver for Integer Linear Programming Problems. CICC (2024)
Siddhartha Raman Sundara Raman, Lizy K. John, Jaydeep P. Kulkarni
SACHI: A Stationarity-Aware, All-Digital, Near-Memory, Ising Architecture. HPCA (2024)
Sumanth N. Karanth, Sirish Oruganti, Meizhi Wang, Jaydeep P. Kulkarni
Randomization Approaches for Secure SAR ADC Design Resilient Against Power Side-Channel Attacks. HOST (2024)
Saikat Chakraborty, Jaydeep P. Kulkarni
Analyzing the Dynamics of Store Mechanism and Data Retention through Transient Simulations in Si/Ge TRAM for Cryogenic Memory Applications. DRC (2024)
Sirish Oruganti, Meizhi Wang, Vishnuvardhan V. Iyer, Yipeng Wang, Mengtian Yang, Raghavan Kumar, Sanu K. Mathew, Jaydeep P. Kulkarni
Power and EM Side-Channel-Attack-Resilient AES-128 Core with Round-Aligned Globally-Synchronous-Locally-Asynchronous Operation Based on Tunable Replica Circuits. ISSCC (2024)
Siddhartha Raman Sundara Raman, Lizy Kurian John, Jaydeep P. Kulkarni
NEM-GNN: DAC/ADC-less, Scalable, Reconfigurable, Graph and Sparsity-Aware Near-Memory Accelerator for Graph Neural Networks. ACM Trans. Archit. Code Optim. 21 (2) (2024)
Yipeng Wang, Mengtian Yang, Shanshan Xie, Meizhi Wang, Jaydeep P. Kulkarni
CIMGN: An Energy-efficient All-digital Compute-in-memory Graph Neural Network Processor. ESSCIRC (2023)
Yipeng Wang, Shanshan Xie, Jacob N. Rohan, Meizhi Wang, Mengtian Yang, Sirish Oruganti, Jaydeep P. Kulkarni
A GNN Computing-in-Memory Macro and Accelerator with Analog-Digital Hybrid Transformation and CAMenabled Search-reduce. CICC (2023)
Rishabh Sehgal, Rishab Mehra, Can Ni, Jaydeep P. Kulkarni
Compute-MLROM: Compute-in-Multi Level Read Only Memory for Energy Efficient Edge AI Inference Engines. ESSCIRC (2023)
Xiangxing Yang, Keren Zhu, Xiyuan Tang, Meizhi Wang, Mingtao Zhan, Nanshu Lu, Jaydeep P. Kulkarni, David Z. Pan, Yongpan Liu, Nan Sun
An In-Memory-Computing Charge-Domain Ternary CNN Classifier. IEEE J. Solid State Circuits 58 (5) (2023)
Shanshan Xie, Mengtian Yang, S. Andrew Lanham, Yipeng Wang, Meizhi Wang, Sirish Oruganti, Jaydeep P. Kulkarni
Snap-SAT: A One-Shot Energy-Performance-Aware All-Digital Compute-in-Memory Solver for Large-Scale Hard Boolean Satisfiability Problems. ISSCC (2023)
Mengtian Yang, Yipeng Wang, Jaydeep P. Kulkarni
3D eDRAM TensorCore Architecture for Large-scale Matrix Multiplication. HiPC (2023)
Naman Maheshwari, Nicholas Malaya, Scott Moe, Jaydeep P. Kulkarni, Sudhanva Gurumurthi
An Estimator for the Sensitivity to Perturbations of Deep Neural Networks. CoRR (2023)
S. S. Teja Nibhanupudi, Sirish Oruganti, Rahul Mathur, Nishant Gupta, Meizhi Wang, Jaydeep P. Kulkarni
Invited: Buried Power Rails and Back-side Power Grids: Prospects and Challenges. DAC (2023)
Rishabh Sehgal, Tanmay Thareja, Shanshan Xie, Can Ni, Jaydeep P. Kulkarni
A Bit-Serial, Compute-in-SRAM Design Featuring Hybrid-Integrating ADCs and Input Dependent Binary Scaled Precharge Eliminating DACs for Energy-Efficient DNN Inference. IEEE J. Solid State Circuits 58 (7) (2023)
Amlan Ghosh, Saroj Satapathy, Jaydeep P. Kulkarni, Prashant D. Joshi
Aging Effects On Clock Gated Memory Phase Paths. DFT (2022)
Stafford Hutchins, Jiabo Li, Atresh Sanne, Zhanping Chen, Mohammad M. Hasan, Uddalak Bhattacharya, Eric Karl, Jaydeep P. Kulkarni
A High Output Power 1V Charge Pump and Power Switch for Configurable, In-Field-Programmable Metal eFuse on Intel 4 Logic Technology. VLSI Technology and Circuits (2022)
Shanshan Xie, Siddhartha Raman Sundara Raman, Can Ni, Meizhi Wang, Mengtian Yang, Jaydeep P. Kulkarni
Ising-CIM: A Reconfigurable and Scalable Compute Within Memory Analog Ising Accelerator for Solving Combinatorial Optimization Problems. IEEE J. Solid State Circuits 57 (11) (2022)
Siddhartha Raman Sundara Raman, S. S. Teja Nibhanupudi, Jaydeep P. Kulkarni
Enabling In-Memory Computations in Non-Volatile SRAM Designs. IEEE J. Emerg. Sel. Topics Circuits Syst. 12 (2) (2022)
Donghyuk Kim, Chengshuo Yu, Shanshan Xie, Yuzong Chen, Joo-Young Kim, Bongjin Kim, Jaydeep P. Kulkarni, Tony Tae-Hyoung Kim
An Overview of Processing-in-Memory Circuits for Artificial Intelligence and Machine Learning. IEEE J. Emerg. Sel. Topics Circuits Syst. 12 (2) (2022)
Tony Tae-Hyoung Kim, Bongjin Kim, Joo-Young Kim, Jaydeep P. Kulkarni
Guest Editorial Revolution of AI and Machine Learning With Processing-in-Memory (PIM): From Systems, Architectures, to Circuits. IEEE J. Emerg. Sel. Topics Circuits Syst. 12 (2) (2022)
Saikat Chakraborty, Jaydeep P. Kulkarni
Buried-Channel Ferroelectric FET as Energy Efficient and Reliable 1T-NVM. DRC (2022)
Meizhi Wang, Sirish Oruganti, Shanshan Xie, Raghavan Kumar, Sanu Mathew, Jaydeep P. Kulkarni
Fine-Grained Electromagnetic Side-Channel Analysis Resilient Secure AES Core with Stacked Voltage Domains and Spatio-temporally Randomized Circuit Blocks. ESSCIRC (2022)
Shanshan Xie, Can Ni, Pulkit Jain, Fatih Hamzaoglu, Jaydeep P. Kulkarni
Gain-Cell CIM: Leakage and Bitline Swing Aware 2T1C Gain-Cell eDRAM Compute in Memory Design with Bitline Precharge DACs and Compact Schmitt Trigger ADCs. VLSI Technology and Circuits (2022)
Rishab Mehra, S. S. Teja Nibhanupudi, Jaydeep P. Kulkarni
Statistical Analysis of 2T1R Gain-Cell RRAM Bitcell for Area Efficient, High-Performance, and Reliable Multi-level Cell Operation. DRC (2022)
S. S. Teja Nibhanupudi, Dmitry Veksler, Anupam Roy, Matthew Coupin, Kevin C. Matthews, Jamie Warner, Gennadi Bersuker, Jaydeep P. Kulkarni, Sanjay K. Banerjee
Experimental demonstration of sub-nanosecond switching in 2D hexagonal Boron Nitride resistive memory devices. DRC (2022)
Saikat Chakraborty, Jaydeep P. Kulkarni
Cryo-TRAM: Gated Thyristor based Capacitor-less DRAM for Cryogenic Computing. DRC (2022)
Rishabh Sehgal, Jaydeep P. Kulkarni
Trends in Analog and Digital Intensive Compute-in-SRAM Designs. AICAS (2021)
Xiangxing Yang, Keren Zhu, Xiyuan Tang, Meizhi Wang, Mingtao Zhan, Nanshu Lu, Jaydeep P. Kulkarni, David Z. Pan, Yongpan Liu, Nan Sun
An In-Memory-Computing Charge-Domain Ternary CNN Classifier. CICC (2021)
Meizhi Wang, Vishnuvardhan V. Iyer, Shanshan Xie, Ge Li, Sanu K. Mathew, Raghavan Kumar, Michael Orshansky, Ali E. Yilmaz, Jaydeep P. Kulkarni
Physical Design Strategies for Mitigating Fine-Grained Electromagnetic Side-Channel Attacks. CICC (2021)
Rahul Mathur, Mudit Bhargava, Heath Perry, Alberto Cestero, Frank Frederick, Shawn Hung, Chien-Ju Chao, Daniel Smith, Daniel Fisher, Norman Robson, Xiaoqing Xu, Pranavi Chandupatla, Raguram Balachandran, Saurabh Sinha, Brian Cline, Jaydeep P. Kulkarni
3D-Split SRAM: Enabling Generational Gains in Advanced CMOS. CICC (2021)
Shanshan Xie, Can Ni, Aseem Sayal, Pulkit Jain, Fatih Hamzaoglu, Jaydeep P. Kulkarni
16.2 eDRAM-CIM: Compute-In-Memory Design with Reconfigurable Embedded-Dynamic-Memory Array Realizing Adaptive Data Converters and Charge-Domain Computing. ISSCC (2021)
Siddhartha Raman Sundara Raman, Shanshan Xie, Jaydeep P. Kulkarni
Compute-in-eDRAM with Backend Integrated Indium Gallium Zinc Oxide Transistors. ISCAS (2021)
Aseem Sayal, Shirin Fathima, S. S. Teja Nibhanupudi, Jaydeep P. Kulkarni
COMPAC: Compressed Time-Domain, Pooling-Aware Convolution CNN Engine With Reduced Data Movement for Energy-Efficient AI Computing. IEEE J. Solid State Circuits 56 (7) (2021)
Meizhi Wang, Shanshan Xie, Ping Na Li, Aseem Sayal, Ge Li, Vishnuvardhan V. Iyer, Aditya Thimmaiah, Michael Orshansky, Ali E. Yilmaz, Jaydeep P. Kulkarni
Galvanically Isolated, Power and Electromagnetic Side-Channel Attack Resilient Secure AES Core with Integrated Charge Pump based Power Management. CICC (2021)
Jacob N. Rohan, Jaydeep P. Kulkarni
Realizing Direct Convolution in Memory with Systolic-RAM. A-SSCC (2021)
Jaydeep P. Kulkarni, Andres Malavasi, Charles Augustine, Carlos Tokunaga, Jim Tschanz, Muhammad M. Khellah, Vivek De
Low Swing and Column Multiplexed Bitline Techniques for Low-Vmin, Noise-Tolerant, High-Density, 1R1W 8T-Bitcell SRAM in 10nm FinFET CMOS. VLSI Circuits (2020)
Aseem Sayal, S. S. Teja Nibhanupudi, Shirin Fathima, Jaydeep P. Kulkarni
A 12.08-TOPS/W All-Digital Time-Domain CNN Engine Using Bi-Directional Memory Delay Lines for Energy Efficient Edge Computing. IEEE J. Solid State Circuits 55 (1) (2020)
Aseem Sayal, Paras Ajay, Mark W. McDermott, S. V. Sreenivasan, Jaydeep P. Kulkarni
M2A2: Microscale Modular Assembled ASICs for High-Mix, Low-Volume, Heterogeneously Integrated Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (12) (2020)
Jaydeep P. Kulkarni
Chip Design 2020. IEEE Micro 40 (6) (2020)
Jacob N. Rohan, Pingping Zhuang, S. S. Teja Nibhanupudi, Sanjay K. Banerjee, Jaydeep P. Kulkarni
Neural Network Assisted Compact Model for Accurate Characterization of Cycle-to-cycle Variations in 2-D $h$-BN based RRAM devices. DRC (2019)
Aseem Sayal, Shirin Fathima, S. S. Teja Nibhanupudi, Jaydeep P. Kulkarni
All-Digital Time-Domain CNN Engine Using Bidirectional Memory Delay Lines for Energy-Efficient Edge Computing. ISSCC (2019)
Subrahmanya Teja, Jaydeep P. Kulkarni
Soft-FET: phase transition material assisted soft switching field effect transistor for supply voltage droop mitigation. DAC (2018)
Seyedhamidreza Motaman, Swaroop Ghosh, Jaydeep P. Kulkarni
VFAB: A Novel 2-Stage STTRAM Sensing Using Voltage Feedback and Boosting. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2018)
Minki Cho, Stephen T. Kim, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De
Postsilicon Voltage Guard-Band Reduction in a 22 nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating. IEEE J. Solid State Circuits 52 (1) (2017)
Jaydeep P. Kulkarni, John Keane, Kyung-Hoae Koo, Satyanand Nalam, Zheng Guo, Eric Karl, Kevin Zhang
1R1W 8T SRAM Arrays Operating Down to 560 mV Utilizing Small-Signal Sensing With Charge Shared Bitline and Asymmetric Sense Amplifier in 14 nm FinFET CMOS Technology. IEEE J. Solid State Circuits 52 (1) (2017)
Krishnendu Chakrabarty, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Rajiv V. Joshi, Tanay Karnik, Mehran Mozaffari Kermani, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep P. Kulkarni, Eren Kursun, Erik Larsson, Hai (Helen) Li, Huawei Li, Patrick P. Mercier, Prabhat Mishra, Makoto Nagata, Arun S. Natarajan, Koji Nii, Partha Pratim Pande, Ioannis Savidis, Mingoo Seok, Sheldon X.-D. Tan, Mark M. Tehranipoor, Aida Todri-Sanial, Miroslav N. Velev, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Stacey Weber Jackson
Editorial. IEEE Trans. Very Large Scale Integr. Syst. 25 (1) (2017)
Jaydeep P. Kulkarni, Carlos Tokunaga, Paolo A. Aseron, Trang Nguyen, Charles Augustine, James W. Tschanz, Vivek De
A 409 GOPS/W Adaptive and Resilient Domino Register File in 22 nm Tri-Gate CMOS Featuring In-Situ Timing Margin and Error Detection for Tolerance to Within-Die Variation, Voltage Droop, Temperature and Aging. IEEE J. Solid State Circuits 51 (1) (2016)
Minki Cho, Stephen T. Kim, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De
8.4 Post-silicon voltage-guard-band reduction in a 22nm graphics execution core using adaptive voltage scaling and dynamic power gating. ISSCC (2016)
Stephen T. Kim, Yi-Chun Shih, Kaushik Mazumdar, Rinkle Jain, Joseph F. Ryan, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De
Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator. IEEE J. Solid State Circuits 51 (1) (2016)
Seyedhamidreza Motaman, Swaroop Ghosh, Jaydeep P. Kulkarni
A novel slope detection technique for robust STTRAM sensing. ISLPED (2015)
Jaydeep P. Kulkarni, Carlos Tokunaga, Paolo A. Aseron, Trang Nguyen, Charles Augustine, James W. Tschanz, Vivek De
4.7 A 409GOPS/W adaptive and resilient domino register file in 22nm tri-gate CMOS featuring in-situ timing margin and error detection for tolerance to within-die variation, voltage droop, temperature and aging. ISSCC (2015)
Stephen T. Kim, Yi-Chun Shih, Kaushik Mazumdar, Rinkle Jain, Joseph F. Ryan, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De
8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation. ISSCC (2015)
Carlos Tokunaga, Joseph F. Ryan, Charles Augustine, Jaydeep P. Kulkarni, Yi-Chun Shih, Stephen T. Kim, Rinkle Jain, Keith A. Bowman, Arijit Raychowdhury, Muhammad M. Khellah, James W. Tschanz, Vivek De
5.7 A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep. ISSCC (2014)
Jaydeep P. Kulkarni, Kaushik Roy
Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design. IEEE Trans. Very Large Scale Integr. Syst. 20 (2) (2012)
Vinay Saripalli, Suman Datta, Vijaykrishnan Narayanan, Jaydeep P. Kulkarni
Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design. NANOARCH (2011)
Jaydeep P. Kulkarni, Ashish Goel, Patrick Ndai, Kaushik Roy
A Read-Disturb-Free, Differential Sensing 1R/1W Port, 8T Bitcell Array. IEEE Trans. Very Large Scale Integr. Syst. 19 (9) (2011)
Mesut Meterelliyoz, Ashish Goel, Jaydeep P. Kulkarni, Kaushik Roy
Accurate characterization of random process variations using a robust low-voltage high-sensitivity sensor featuring replica-bias circuit. ISSCC (2010)
Mesut Meterelliyoz, Peilin Song, Franco Stellari, Jaydeep P. Kulkarni, Kaushik Roy
Characterization of Random Process Variations Using Ultralow-Power, High-Sensitivity, Bias-Free Sub-Threshold Process Sensor. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2010)
Mesut Meterelliyoz, Jaydeep P. Kulkarni, Kaushik Roy
Analysis of SRAM and eDRAM Cache Memories Under Spatial Temperature Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (1) (2010)
Kaushik Roy, Jaydeep P. Kulkarni, Sumeet Kumar Gupta
Device/circuit interactions at 22nm technology node. DAC (2009)
Ashish Goel, Patrick Ndai, Jaydeep P. Kulkarni, Kaushik Roy
REad/access-preferred (REAP) SRAM - architecture-aware bit cell design for improved yield and lower VMIN. CICC (2009)
Jaydeep P. Kulkarni, Keejong Kim, Sang Phill Park, Kaushik Roy
Process variation tolerant SRAM array for ultra low voltage applications. DAC (2008)
Mesut Meterelliyoz, Jaydeep P. Kulkarni, Kaushik Roy
Thermal analysis of 8-T SRAM for nano-scaled technologies. ISLPED (2008)
Mesut Meterelliyoz, Peilin Song, Franco Stellari, Jaydeep P. Kulkarni, Kaushik Roy
A high sensitivity process variation sensor utilizing sub-threshold operation. CICC (2008)
Jaydeep P. Kulkarni, Kaushik Roy
A High Performance, Scalable Multiplexed Keeper Technique. ISQED (2007)
Jaydeep P. Kulkarni, Keejong Kim, Kaushik Roy
A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM. IEEE J. Solid State Circuits 42 (10) (2007)
Jaydeep P. Kulkarni, Keejong Kim, Kaushik Roy
A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM. ISLPED (2007)
Sameer A. Kibey, Jaydeep P. Kulkarni, Piyush D. Sarode
A Fast LSF Search Algorithm Based on Interframe Correlation in G.723.1. EURASIP J. Adv. Signal Process. 2004 (8) (2004)