8.4 Post-silicon voltage-guard-band reduction in a 22nm graphics execution core using adaptive voltage scaling and dynamic power gating.
Minki ChoStephen T. KimCarlos TokunagaCharles AugustineJaydeep P. KulkarniKrishnan RavichandranJames W. TschanzMuhammad M. KhellahVivek DePublished in: ISSCC (2016)
Keyphrases
- power consumption
- clock gating
- power losses
- power system
- liquid crystal
- duty cycle
- electrical power
- reactive power
- single phase
- metal oxide
- power quality
- high voltage
- dynamically adjust
- active power
- energy dissipation
- power supply
- transmission line
- low voltage
- electric field
- transmission electron microscopy
- multimedia
- field effect transistors
- power generation
- power management
- power flow
- electrical properties
- computer graphics
- dynamic environments
- high speed
- low cost
- cmos technology