A Bit-Serial, Compute-in-SRAM Design Featuring Hybrid-Integrating ADCs and Input Dependent Binary Scaled Precharge Eliminating DACs for Energy-Efficient DNN Inference.
Rishabh SehgalTanmay TharejaShanshan XieCan NiJaydeep P. KulkarniPublished in: IEEE J. Solid State Circuits (2023)