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Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design.
Vinay Saripalli
Suman Datta
Vijaykrishnan Narayanan
Jaydeep P. Kulkarni
Published in:
NANOARCH (2011)
Keyphrases
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engineering design
real time
building blocks
ultra low power
database
case study
computer aided
neural network
artificial intelligence
high speed
low power
design space
design considerations