Power-Efficient Dual-Supply 64kB L1 Caches in a 65nm CMOS Technology.

Brian Campbell James Burnette Naveen Javarappa Vincent von Kaenel

Published in: CICC (2007)

Keyphrases

cmos technology
power consumption
low power
silicon on insulator
power dissipation
knowledge base
parallel processing
spl times
image processing
power management
low voltage