Yajun Ran

Publication Activity (10 Years)

Years Active: 2003-2007
Publications (10 Years): 0

Publications

Darsun Tsiena, Chien Kuo Wang, William W. J. Wang, Yajun Ran, Philippe Hurat, Nishath Verghese
Context-specific leakage and delay analysis of a 65nm standard cell library for lithography-induced variability. SoCC (2007)
Yajun Ran, Malgorzata Marek-Sadowska
Designing via-configurable logic blocks for regular fabric. IEEE Trans. Very Large Scale Integr. Syst. 14 (1) (2006)
Yajun Ran, Malgorzata Marek-Sadowska
Via-Configurable Routing Architectures and Fast Design Mappability Estimation for Regular Fabrics. IEEE Trans. Very Large Scale Integr. Syst. 14 (9) (2006)
Kai Wang, Yajun Ran, Hailin Jiang, Malgorzata Marek-Sadowska
General skew constrained clock network sizing based on sequential linear programming. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (5) (2005)
Yajun Ran, Malgorzata Marek-Sadowska
Via-configurable routing architectures and fast design mappability estimation for regular fabrics. ICCAD (2005)
Yajun Ran, Alex Kondratyev, Kenneth H. Tseng, Yosinori Watanabe, Malgorzata Marek-Sadowska
Eliminating false positives in crosstalk noise analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (9) (2005)
Yajun Ran, Malgorzata Marek-Sadowska
The Magic of a Via-Configurable Regular Fabric. ICCD (2004)
Yajun Ran, Malgorzata Marek-Sadowska
An integrated design flow for a via-configurable gate array. ICCAD (2004)
Yajun Ran, Malgorzata Marek-Sadowska
Designing a via-configurable regular fabric. CICC (2004)
Yajun Ran, Malgorzata Marek-Sadowska
On designing via-configurable cell blocks for regular fabrics. DAC (2004)
Yajun Ran, Alex Kondratyev, Yosinori Watanabe, Malgorzata Marek-Sadowska
Eliminating False Positives in Crosstalk Noise Analysis. DATE (2004)
Yajun Ran, Malgorzata Marek-Sadowska
Crosstalk noise in FPGAs. DAC (2003)
Donald Chai, Alex Kondratyev, Yajun Ran, Kenneth H. Tseng, Yosinori Watanabe, Malgorzata Marek-Sadowska
Temporofunctional crosstalk noise analysis. DAC (2003)