Thomas R. Shiple

Publication Activity (10 Years)

Years Active: 1989-2012
Publications (10 Years): 0

Top Topics

Simulation Models

Colored Petri Nets

Top Venues

Formal Methods Syst. Des.

Publications

Michael Mendler, Thomas R. Shiple, Gérard Berry
Constructive Boolean circuits and the exactness of timed ternary simulation. Formal Methods Syst. Des. 40 (3) (2012)
Stephen M. Plaza, Prashant Saxena, Thomas R. Shiple, Pei-Hsin Ho
Multi-mode redundancy removal. ISQED (2011)
In-Ho Moon, Hee-Hwan Kwak, James H. Kukula, Thomas R. Shiple, Carl Pixley
Simplifying Circuits for Formal Verification Using Parametric Representation. FMCAD (2002)
Hee-Hwan Kwak, In-Ho Moon, James H. Kukula, Thomas R. Shiple
Combinational equivalence checking through function transformation. ICCAD (2002)
Adnan Aziz, Thomas R. Shiple, Vigyan Singhal, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
Formula-Dependent Equivalence for Compositional CTL Model Checking. Formal Methods Syst. Des. 21 (2) (2002)
Pankaj Chauhan, Edmund M. Clarke, Somesh Jha, James H. Kukula, Thomas R. Shiple, Helmut Veith, Dong Wang
Non-linear Quantification Scheduling in Image Computation. ICCAD (2001)
Adnan Aziz, James H. Kukula, Thomas R. Shiple, Jun Yuan
Efficient control state-space search. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20 (2) (2001)
Pei-Hsin Ho, Thomas R. Shiple, Kevin Harer, James H. Kukula, Robert F. Damiano, Valeria Bertacco, Jerry Taylor, Jiang Long
Smart Simulation Using Collaborative Formal and Simulation Engines. ICCAD (2000)
James H. Kukula, Thomas R. Shiple
Building Circuits from Relations. CAV (2000)
In-Ho Moon, James H. Kukula, Thomas R. Shiple, Fabio Somenzi
Least fixpoint approximations for reachability analysis. ICCAD (1999)
Kavita Ravi, Kenneth L. McMillan, Thomas R. Shiple, Fabio Somenzi
Approximation and Decomposition of Binary Decision Diagrams. DAC (1998)
Adnan Aziz, James H. Kukula, Thomas R. Shiple
Hybrid Verification Using Saturated Simulation. DAC (1998)
James H. Kukula, Thomas R. Shiple, Adnan Aziz
Techniques for Implicit State Enumeration of EFSMs. FMCAD (1998)
Thomas R. Shiple, James H. Kukula, Rajeev K. Ranjan
A Comparison of Presburger Engines for EFSM Reachability. CAV (1998)
Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa
VIS: A System for Verification and Synthesis. CAV (1996)
Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa
VIS. FMCAD (1996)
Thomas R. Shiple, Gérard Berry, Hervé J. Touati
Constructive Analysis of Cyclic Circuits. ED&TC (1996)
Kevin Covey, Sandra Murdock, Thomas R. Shiple
Two-phase Logic Design by Hardware Flowcharts. ICCD (1994)
Adnan Aziz, Thomas R. Shiple, Vigyan Singhal
Formula-Dependent Equivalence for Compositional CTL Model Checking. CAV (1994)
Thomas R. Shiple, Ramin Hojati, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton
Heuristic Minimization of BDDs Using Don't Cares. DAC (1994)
Adnan Aziz, Felice Balarin, Szu-Tsung Cheng, Ramin Hojati, Timothy Kam, Sriram C. Krishnan, Rajeev K. Ranjan, Thomas R. Shiple, Vigyan Singhal, Serdar Tasiran, Huey-Yih Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
HSIS: A BDD-Based Environment for Formal Verification. DAC (1994)
Ramin Hojati, Thomas R. Shiple, Robert K. Brayton, Robert P. Kurshan
A Unified Approach to Language Containment and Fair CTL Model Checking. DAC (1993)
Massimiliano Chiodo, Thomas R. Shiple, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton
Automatic compositional minimization in CTL model checking. ICCAD (1992)
Thomas R. Shiple, Massimiliano Chiodo, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton
Automatic Reduction in CTL Compositional Model Checking. CAV (1992)
Antun Domic, Samuel Levitin, Nathan Phillips, Channeary Thai, Thomas R. Shiple, Dilip Bhavsar, Clint Bissel
CLEO: a CMOS layout generator. ICCAD (1989)