Albert R. Wang

Publication Activity (10 Years)

Years Active: 1987-2001
Publications (10 Years): 0

Publications

Ying Zhao, Sharad Malik, Albert R. Wang, Matthew W. Moskewicz, Conor F. Madigan
Matching Architecture to Application Via Configurable Processors: A Case Study with Boolean Satisfiability Problem. ICCD (2001)
Stan Y. Liao, Srinivas Devadas, Kurt Keutzer, Steven W. K. Tjiang, Albert R. Wang
Code Optimization Techniques in Embedded DSP Microprocessors. Des. Autom. Embed. Syst. 3 (1) (1998)
Stan Y. Liao, Srinivas Devadas, Kurt Keutzer, Steven W. K. Tjiang, Albert R. Wang
Storage Assignment to Decrease Code Size. ACM Trans. Program. Lang. Syst. 18 (3) (1996)
Peter Vanbekbergen, Albert R. Wang, Kurt Keutzer
A Design and Validation System for Asynchronous Circuits. DAC (1995)
Stan Y. Liao, Srinivas Devadas, Kurt Keutzer, Steven W. K. Tjiang, Albert R. Wang
Code Optimization Techniques for Embedded DSP Microprocessors. DAC (1995)
Stan Y. Liao, Srinivas Devadas, Kurt Keutzer, Steven W. K. Tjiang, Albert R. Wang
Storage Assignment to Decrease Code Size. PLDI (1995)
Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert R. Wang
Event suppression: improving the efficiency of timing simulation for synchronous digital circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13 (6) (1994)
Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert R. Wang
Verification of asynchronous interface circuits with bounded wire delays. J. VLSI Signal Process. 7 (1-2) (1994)
Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert R. Wang
Certified timing verification and the transition delay of a logic circuit. IEEE Trans. Very Large Scale Integr. Syst. 2 (3) (1994)
Guido Araujo, Srinivas Devadas, Kurt Keutzer, Stan Y. Liao, Sharad Malik, Ashok Sudarsanam, Steven W. K. Tjiang, Albert R. Wang
Challenges in code generation for embedded processors. Code Generation for Embedded Processors (1994)
Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert R. Wang
Computation of floating mode delay in combinational circuits: practice and implementation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 (12) (1993)
Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert R. Wang
Verification of asynchronous interface circuits with bounded wire delays. ICCAD (1992)
Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert R. Wang
Certified Timing Verification and the Transition Delay of a Logic Circuit. DAC (1992)
Alexander Saldanha, Albert R. Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
Multi-level Logic Simplification Using Don't Cares and Filters. DAC (1989)
Karen A. Bartlett, Robert K. Brayton, Gary D. Hachtel, Reily M. Jacoby, Christopher R. Morrison, Richard L. Rudell, Alberto L. Sangiovanni-Vincentelli, Albert R. Wang
Multi-level logic minimization using implicit don't cares. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7 (6) (1988)
Sharad Malik, Albert R. Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
Logic verification using binary decision diagrams in a logic synthesis environment. ICCAD (1988)
Srinivas Devadas, Albert R. Wang, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli
Boolean decomposition in multi-level logic optimization. ICCAD (1988)
Kanwar Jit Singh, Albert R. Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
Timing optimization of combinational logic. ICCAD (1988)
Robert K. Brayton, Richard L. Rudell, Alberto L. Sangiovanni-Vincentelli, Albert R. Wang
MIS: A Multiple-Level Logic Optimization System. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6 (6) (1987)