Verification of asynchronous interface circuits with bounded wire delays.

Srinivas Devadas Kurt Keutzer Sharad Malik Albert R. Wang

Published in: ICCAD (1992)

Keyphrases

asynchronous circuits
delay insensitive
model checking
high level synthesis
user interface
shift register
high speed
interface design
user friendly
graphical interface
state machines
visual interface
direct manipulation
digital circuits
real time
data sets
formal verification
low cost
digital libraries
round trip