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Certified timing verification and the transition delay of a logic circuit.
Srinivas Devadas
Kurt Keutzer
Sharad Malik
Albert R. Wang
Published in:
IEEE Trans. Very Large Scale Integr. Syst. (1994)
Keyphrases
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asynchronous circuits
delay insensitive
model checking
logic synthesis
digital circuits
power dissipation
logic circuits
micron cmos
circuit design
signature verification
predicate logic
multi valued
inference rules
logic programming
high speed
linear time temporal logic
real time