Certified Timing Verification and the Transition Delay of a Logic Circuit.
Srinivas DevadasKurt KeutzerSharad MalikAlbert R. WangPublished in: DAC (1992)
Keyphrases
- asynchronous circuits
- delay insensitive
- model checking
- logic circuits
- digital circuits
- power dissipation
- logic synthesis
- verification method
- chip design
- high speed
- power consumption
- low power
- circuit design
- formal verification
- phase locked loop
- neural network
- electronic circuits
- automated reasoning
- logic programming
- low cost