Symbolic timing analysis and resynthesis for low power of combinational circuits containing false paths.
R. Iris BaharHyunwoo ChoGary D. HachtelEnrico MaciiFabio SomenziPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (1997)
Keyphrases
- low power
- logic circuits
- high speed
- power consumption
- low cost
- power dissipation
- cmos technology
- single chip
- digital signal processing
- high power
- vlsi circuits
- delay insensitive
- mixed signal
- vlsi architecture
- gate array
- power reduction
- real time
- low power consumption
- shortest path
- wireless transmission
- image sensor
- image processing