Tali Moreshet

Publication Activity (10 Years)

Years Active: 2003-2022
Publications (10 Years): 11

Top Topics

Arithmetic Operations

Energy Efficiency

Speculative Execution

Top Venues

ACM Trans. Embed. Comput. Syst.

Publications

Jiwon Choe, Andrew Crotty, Tali Moreshet, Maurice Herlihy, R. Iris Bahar
HybriDS: Cache-Conscious Concurrent Data Structures for Near-Memory Processing Architectures. SPAA (2022)
Samuel Thomas, Jiwon Choe, Ofir Gordon, Erez Petrank, Tali Moreshet, Maurice Herlihy, R. Iris Bahar
Towards Hardware Accelerated Garbage Collection with Near-Memory Processing. HPEC (2022)
Zamshed I. Chowdhury, S. Karen Khatamifard, Zhaoyong Zheng, Tali Moreshet, R. Iris Bahar, Ulya R. Karpuzcu
Voltage Noise Mitigation With Barrier Approximation. IEEE Comput. Archit. Lett. 19 (2) (2020)
Jiwon Choe, Amy Huang, Tali Moreshet, Maurice Herlihy, R. Iris Bahar
Concurrent Data Structures with Near-Data-Processing: an Architecture-Aware Implementation. SPAA (2019)
Zamshed I. Chowdhury, S. Karen Khatamifard, Zhaoyong Zheng, Tali Moreshet, R. Iris Bahar, Ulya R. Karpuzcu
Barrier Synchronization vs. Voltage Noise: A Quantitative Analysis. IISWC (2019)
Dimitra Papagiannopoulou, Sungseob Whang, Tali Moreshet, R. Iris Bahar
IgnoreTM: Opportunistically Ignoring Timing Violations for Energy Savings using HTM. DATE (2019)
Jiwon Choe, Tali Moreshet, R. Iris Bahar, Maurice Herlihy
Attacking memory-hard scrypt with near-data-processing. MEMSYS (2019)
Dimitra Papagiannopoulou, Andrea Marongiu, Tali Moreshet, Luca Benini, Maurice Herlihy, R. Iris Bahar
Hardware Transactional Memory Exploration in Coherence-Free Many-Core Architectures. Int. J. Parallel Program. 46 (6) (2018)
Sungseob Whang, Tymani Rachford, Dimitra Papagiannopoulou, Tali Moreshet, R. Iris Bahar
Evaluating critical bits in arithmetic operations due to timing violations. HPEC (2017)
Dimitra Papagiannopoulou, Andrea Marongiu, Tali Moreshet, Maurice Herlihy, R. Iris Bahar
Edge-TM: Exploiting Transactional Memory for Error Tolerance and Energy Efficiency. ACM Trans. Embed. Comput. Syst. 16 (5s) (2017)
Thomas Carle, Dimitra Papagiannopoulou, Tali Moreshet, Andrea Marongiu, Maurice Herlihy, R. Iris Bahar
Thrifty-malloc: A HW/SW codesign for the dynamic management of hardware transactional memory in embedded multicore systems. CASES (2016)
Dimitra Papagiannopoulou, Andrea Marongiu, Tali Moreshet, Luca Benini, Maurice Herlihy, R. Iris Bahar
Playing with Fire: Transactional Memory Revisited for Error-Resilient and Energy-Efficient MPSoC Execution. ACM Great Lakes Symposium on VLSI (2015)
Dimitra Papagiannopoulou, Giuseppe Capodanno, Tali Moreshet, Maurice Herlihy, R. Iris Bahar
Energy-Efficient and High-Performance Lock Speculation Hardware for Embedded Multicore Systems. ACM Trans. Embed. Comput. Syst. 14 (3) (2015)
Dimitra Papagiannopoulou, Tali Moreshet, Andrea Marongiu, Luca Benini, Maurice Herlihy, R. Iris Bahar
Speculative synchronization for coherence-free embedded NUMA architectures. ICSAMOS (2014)
Dimitra Papagiannopoulou, R. Iris Bahar, Tali Moreshet, Maurice Herlihy, Andrea Marongiu, Luca Benini
Transparent and energy-efficient speculation on NUMA architectures for embedded MPSoCs. MES (2013)
Fuat Keceli, Tali Moreshet, Uzi Vishkin
Power-Performance Comparison of Single-Task Driven Many-Cores. ICPADS (2011)
Cesare Ferri, Andrea Marongiu, Benjamin Lipton, R. Iris Bahar, Tali Moreshet, Luca Benini, Maurice Herlihy
SoC-TM: integrated HW/SW support for transactional memory programming on embedded MPSoCs. CODES+ISSS (2011)
Cesare Ferri, Samantha Wood, Tali Moreshet, R. Iris Bahar, Maurice Herlihy
Embedded-TM: Energy and complexity-effective hardware transactional memory for embedded multicore systems. J. Parallel Distributed Comput. 70 (10) (2010)
Fuat Keceli, Tali Moreshet, Uzi Vishkin
Thermal Management of a Many-Core Processor under Fine-Grained Parallelism. Euro-Par Workshops (1) (2010)
Cesare Ferri, Samantha Wood, Tali Moreshet, R. Iris Bahar, Maurice Herlihy
Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems. HiPEAC (2010)
Cesare Ferri, Amber Viescas, Tali Moreshet, R. Iris Bahar, Maurice Herlihy
Energy efficient synchronization techniques for embedded architectures. ACM Great Lakes Symposium on VLSI (2008)
Cesare Ferri, Tali Moreshet, R. Iris Bahar, Luca Benini, Maurice Herlihy
A hardware/software framework for supporting transactional memory in a MPSoC environment. SIGARCH Comput. Archit. News 35 (1) (2007)
Tali Moreshet, R. Iris Bahar, Maurice Herlihy
Energy implications of multiprocessor synchronization. SPAA (2006)
Tali Moreshet, R. Iris Bahar, Maurice Herlihy
Energy reduction in multiprocessor systems using transactional memory. ISLPED (2005)
Tali Moreshet, R. Iris Bahar
Effects of speculation on performance and issue queue design. IEEE Trans. Very Large Scale Integr. Syst. 12 (10) (2004)
Tali Moreshet, R. Iris Bahar
Power-aware issue queue design for speculative instructions. DAC (2003)