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Run-time self-tuning banked loop buffer architecture for power optimization of dynamic workload applications.
Antonio Artés
José Luis Ayala
Ashoka Visweswara Sathanur
Jos Huisken
Francky Catthoor
Published in:
VLSI-SoC (2011)
Keyphrases
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dynamic optimization
optimization problems
optimization algorithm
multi layer
neural network
management system
power consumption
software architecture
constrained optimization
global optimization
real time
response time
combinatorial optimization
data management
optimization model
power management
data sets