Login / Signup
Activity profile driven simultaneous vt assignment and power switch sizing for leakage power minimization in nanometer CMOS designs.
Ashoka Visweswara Sathanur
Jos Huisken
Jan Stuyt
Harmke de Groot
Published in:
ICECS (2010)
Keyphrases
</>
power consumption
high speed
neural network
image processing
artificial neural networks
low power
computational power
power distribution
power losses
data sets
genetic algorithm
hidden markov models
human activities
design space