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Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology.

Andrea CalimeraAntonio PulliniAshoka Visweswara SathanurLuca BeniniAlberto MaciiEnrico MaciiMassimo Poncino
Published in: ACM Great Lakes Symposium on VLSI (2007)
Keyphrases
  • power dissipation
  • nm technology
  • power consumption
  • low power
  • case study
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  • user interface
  • design process
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  • active contours
  • conceptual model