Login / Signup

On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits.

Ashoka Visweswara SathanurAndrea CalimeraAntonio PulliniLuca BeniniAlberto MaciiEnrico MaciiMassimo Poncino
Published in: ISCAS (2008)
Keyphrases
  • power consumption
  • high speed
  • power dissipation
  • chip design
  • circuit design
  • power management
  • neural network
  • low power
  • computational power
  • analog vlsi