Jae-Seok Yang

Publication Activity (10 Years)

Years Active: 2003-2013
Publications (10 Years): 0

Top Topics

Evolutionary Algorithm

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Krit Athikulwongse, Jae-Seok Yang, David Z. Pan, Sung Kyu Lim
Impact of Mechanical Stress on the Full Chip Timing for Through-Silicon-Via-based 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (6) (2013)
Bei Yu, Jhih-Rong Gao, Duo Ding, Yongchan Ban, Jae-Seok Yang, Kun Yuan, Minsik Cho, David Z. Pan
Dealing with IC manufacturability in extreme scaling (Embedded tutorial paper). ICCAD (2012)
David Z. Pan, Sung Kyu Lim, Krit Athikulwongse, Moongon Jung, Joydeep Mitra, Jiwoo Pak, Mohit Pathak, Jae-Seok Yang
Design for manufacturability and reliability for TSV-based 3D ICs. ASP-DAC (2012)
Yongchan Ban, Jae-Seok Yang
Layout aware line-edge roughness modeling and poly optimization for leakage minimization. DAC (2011)
Jae-Seok Yang, Jiwoo Pak, Xin Zhao, Sung Kyu Lim, David Z. Pan
Robust Clock Tree Synthesis with timing yield optimization for 3D-ICs. ASP-DAC (2011)
Wooyoung Jang, Ou He, Jae-Seok Yang, David Z. Pan
Chemical-mechanical polishing aware application-specific 3D NoC design. ICCAD (2011)
Krit Athikulwongse, Ashutosh Chakraborty, Jae-Seok Yang, David Z. Pan, Sung Kyu Lim
Stress-driven 3D-IC placement with TSV keep-out zone and regularity study. ICCAD (2010)
Jae-Seok Yang, Katrina Lu, Minsik Cho, Kun Yuan, David Z. Pan
A new graph-theoretic, multi-objective layout decomposition framework for double patterning lithography. ASP-DAC (2010)
Kun Yuan, Jae-Seok Yang, David Z. Pan
Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (2) (2010)
Jae-Seok Yang, Krit Athikulwongse, Young-Joon Lee, Sung Kyu Lim, David Z. Pan
TSV stress aware timing analysis with applications to 3D-IC layout optimization. DAC (2010)
Kun Yuan, Jae-Seok Yang, David Z. Pan
Double patterning layout decomposition for simultaneous conflict and stitch minimization. ISPD (2009)
Jae-Seok Yang, David Z. Pan
Overlay aware interconnect and timing variation modeling for double patterning technology. ICCAD (2008)
Jae-Seok Yang, Andrew R. Neureuther
Crosstalk Noise Variation Assessment and Analysis for the Worst Process Corner. ISQED (2008)
Jae-Seok Yang, Jeong-Yeol Kim, Joon-Ho Choi, Moon-Hyun Yoo, Jeong-Taek Kong
Elimination of false aggressors using the functional relationship for full-chip crosstalk analysis. ISQED (2003)