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Impact of Mechanical Stress on the Full Chip Timing for Through-Silicon-Via-based 3-D ICs.

Krit AthikulwongseJae-Seok YangDavid Z. PanSung Kyu Lim
Published in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2013)
Keyphrases
  • high speed
  • high density
  • low cost
  • cmos technology
  • vlsi implementation
  • data sets
  • single chip
  • analog vlsi
  • real time
  • wireless sensor networks
  • level parallelism
  • metal oxide semiconductor