Tung-Chieh Chen

Publication Activity (10 Years)

Years Active: 2005-2024
Publications (10 Years): 11

Top Topics

Convolutional Neural Network

Advanced Technology

Ultra Large Scale

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Tung-Chieh Chen
Introduction to the Panel on EDA Challenges at Advanced Technology Nodes. ISPD (2024)
Fu-Chieh Chang, Yu-Wei Tseng, Ya-Wen Yu, Ssu-Rui Lee, Alexandru Cioba, I-Lun Tseng, Da-Shan Shiu, Jhih-Wei Hsu, Cheng-Yuan Wang, Chien-Yi Yang, Ren-Chu Wang, Yao-Wen Chang, Tai-Chen Chen, Tung-Chieh Chen
Flexible Multiple-Objective Reinforcement Learning for Chip Placement. CoRR (2022)
Fu-Chieh Chang, Yu-Wei Tseng, Ya-Wen Yu, Ssu-Rui Lee, Alexandru Cioba, I-Lun Tseng, Da-Shan Shiu, Jhih-Wei Hsu, Cheng-Yuan Wang, Chien-Yi Yang, Ren-Chu Wang, Yao-Wen Chang, Tai-Chen Chen, Tung-Chieh Chen
Flexible chip placement via reinforcement learning: late breaking results. DAC (2022)
Yun Chou, Jhih-Wei Hsu, Yao-Wen Chang, Tung-Chieh Chen
VLSI Structure-aware Placement for Convolutional Neural Network Accelerator Units. DAC (2021)
Tai-Chen Chen, Pei-Yu Lee, Tung-Chieh Chen
Automatic Floorplanning for AI SoCs. VLSI-DAT (2020)
Yen-Chun Liu, Tung-Chieh Chen, Yao-Wen Chang, Sy-Yen Kuo
MDP-trees: multi-domain macro placement for ultra large-scale mixed-size designs. ASP-DAC (2019)
Chau-Chin Huang, Hsin-Ying Lee, Bo-Qiao Lin, Sheng-Wei Yang, Chin-Hao Chang, Szu-To Chen, Yao-Wen Chang, Tung-Chieh Chen, Ismail Bustany
NTUplace4dr: A Detailed-Routing-Driven Placer for Mixed-Size Circuit Designs With Technology and Region Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (3) (2018)
Pei-Yu Lee, Iris Hui-Ru Jiang, Tung-Chieh Chen
FastPass: Fast timing path search for generalized timing exception handling. ASP-DAC (2018)
Szu-To Chen, Yao-Wen Chang, Tung-Chieh Chen
An integrated-spreading-based macro-refining algorithm for large-scale mixed-size circuit designs. ICCAD (2017)
Sheng-Wei Yang, Yao-Wen Chang, Tung-Chieh Chen
Blockage-aware terminal propagation for placement wirelength minimization. ICCAD (2017)
Chin-Hao Chang, Yao-Wen Chang, Tung-Chieh Chen
A novel damped-wave framework for macro placement. ICCAD (2017)
Shih-Ying Liu, Tung-Chieh Chen, Hung-Ming Chen
An approach to anchoring and placing high performance custom digital designs. ASP-DAC (2015)
Po-Hsun Wu, Mark Po-Hung Lin, Tung-Chieh Chen, Ching-Feng Yeh, Xin Li, Tsung-Yi Ho
A Novel Analog Physical Synthesis Methodology Integrating Existent Design Expertise. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (2) (2015)
Po-Cheng Pan, Ching-Yu Chin, Hung-Ming Chen, Tung-Chieh Chen, Chin-Chieh Lee, Jou-Chun Lin
A Fast Prototyping Framework for Analog Layout Migration With Planar Preservation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (9) (2015)
Meng-Kai Hsu, Yi-Fang Chen, Chau-Chin Huang, Sheng Chou, Tzu-Hen Lin, Tung-Chieh Chen, Yao-Wen Chang
NTUplace4h: A Novel Routability-Driven Placement Algorithm for Hierarchical Mixed-Size Circuit Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (12) (2014)
Po-Hsun Wu, Mark Po-Hung Lin, Tung-Chieh Chen, Ching-Feng Yeh, Tsung-Yi Ho, Bin-Da Liu
Exploring Feasibilities of Symmetry Islands and Monotonic Current Paths in Slicing Trees for Analog Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (6) (2014)
Hsing-Chih Chang Chien, Hung-Chih Ou, Tung-Chieh Chen, Ta-Yu Kuan, Yao-Wen Chang
Double patterning lithography-aware analog placement. DAC (2013)
Meng-Kai Hsu, Yi-Fang Chen, Chau-Chin Huang, Tung-Chieh Chen, Yao-Wen Chang
Routability-driven placement for hierarchical mixed-size circuit designs. DAC (2013)
Ching-Yu Chin, Po-Cheng Pan, Hung-Ming Chen, Tung-Chieh Chen, Jou-Chun Lin
Efficient analog layout prototyping by layout reuse with routing preservation. ICCAD (2013)
Po-Hsun Wu, Mark Po-Hung Lin, Tung-Chieh Chen, Tsung-Yi Ho, Yu-Chuan Chen
Lithography-aware 1-dimensional cell generation. ECCTD (2013)
Po-Hsun Wu, Mark Po-Hung Lin, Tung-Chieh Chen, Tsung-Yi Ho, Yu-Chuan Chen, Shun-Ren Siao, Shu-Hung Lin
1-D Cell Generation With Printability Enhancement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (3) (2013)
Po-Hsun Wu, Mark Po-Hung Lin, Yang-Ru Chen, Bing-Shiun Chou, Tung-Chieh Chen, Tsung-Yi Ho, Bin-Da Liu
Performance-driven analog placement considering monotonic current paths. ICCAD (2012)
Tung-Chieh Chen, Ta-Yu Kuan, Chung-Che Hsieh, Chi-Chen Peng
Challenges and solutions in modern analog placement. VLSI-DAT (2012)
Yi-Peng Weng, Hung-Ming Chen, Tung-Chieh Chen, Po-Cheng Pan, Chien-Hung Chen, Wei-Zen Chen
Fast analog layout prototyping for nanometer design migration. ICCAD (2011)
Tung-Chieh Chen
Automated placement for custom digital designs. ISPD (2011)
Yao-Wen Chang, Zhe-Wei Jiang, Tung-Chieh Chen
Essential Issues in Analytical Placement Algorithms. IPSJ Trans. Syst. LSI Des. Methodol. 2 (2009)
Tung-Chieh Chen, Zhe-Wei Jiang, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang
NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (7) (2008)
Tung-Chieh Chen, Yi-Lin Chuang, Yao-Wen Chang
Effective Wire Models for X-Architecture Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (4) (2008)
Tung-Chieh Chen, Ashutosh Chakraborty, David Z. Pan
An integrated nonlinear placement framework with congestion and porosity aware buffer planning. DAC (2008)
Tung-Chieh Chen, Minsik Cho, David Z. Pan, Yao-Wen Chang
Metal-Density-Driven Placement for CMP Variation and Routability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (12) (2008)
Tung-Chieh Chen, Minsik Cho, David Z. Pan, Yao-Wen Chang
Metal-density driven placement for cmp variation and routability. ISPD (2008)
Tung-Chieh Chen, Ping-Hung Yuh, Yao-Wen Chang, Few-Juh Huang, T.-Y. Liu
MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (9) (2008)
Tung-Chieh Chen, Yao-Wen Chang, Shyh-Chang Lin
A New Multilevel Framework for Large-Scale Interconnect-Driven Floorplanning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (2) (2008)
Tung-Chieh Chen, Ping-Hung Yuh, Yao-Wen Chang, Fwu-Juh Huang, Denny Liu
MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size Designs. DAC (2007)
Tung-Chieh Chen, Yi-Lin Chuang, Yao-Wen Chang
X-architecture placement based on effective wire models. ISPD (2007)
Tung-Chieh Chen, Zhe-Wei Jiang, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang
A high-quality mixed-size analytical placer considering preplaced blocks and density constraints. ICCAD (2006)
Zhe-Wei Jiang, Tung-Chieh Chen, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang
NTUplace2: a hybrid placer using partitioning and analytical techniques. ISPD (2006)
Tung-Chieh Chen, Yao-Wen Chang
-Tree and Fast Simulated Annealing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (4) (2006)
Tung-Chieh Chen, Yao-Wen Chang, Shyh-Chang Lin
IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs. ICCAD (2005)
Jen-Yi Wuu, Tung-Chieh Chen, Yao-Wen Chang
SoC test scheduling using the B-tree based floorplanning technique. ASP-DAC (2005)
Tung-Chieh Chen, Tien-Chang Hsu, Zhe-Wei Jiang, Yao-Wen Chang
NTUplace: a ratio partitioning based placement algorithm for large-scale mixed-size designs. ISPD (2005)
Tung-Chieh Chen, Yao-Wen Chang
Modern floorplanning based on fast simulated annealing. ISPD (2005)