Yu-Chuan Chen

Publication Activity (10 Years)

Years Active: 2013-2024
Publications (10 Years): 8

Top Topics

Polynomial Approximation

Outcome Prediction

Ischemic Stroke

Top Venues

Int. Trans. Oper. Res.

Publications

Yu-Chuan Chen, Jen-Ya Wang
A Lower Bound for Minimizing Waiting Time in Coexisting Virtual and Physical Worlds. IEEE Access 12 (2024)
Yeong-Yuh Xu, Pao-Sheng Yen, Yu-Hui Lin, Chung-Yu Lai, Yu-Chuan Chen, Chuan-Kang Liu
Machine Learning-Based Outcome Prediction of Acute Ischemic Stroke After Endovascular Treatment. BCD (2023)
Jau-Ji Shen, Chin-Feng Lee, Yu-Chuan Chen, Somya Agrawal
Unsupervised Defect Detection based on Boundary Equilibrium Generative Adversarial Network. ICFET (2020)
Yu-Chuan Chen, Yung-Ho Chiu, Ching-Jen Chiu
The performance evaluation of banks considering risk: an application of undesirable relation network DEA. Int. Trans. Oper. Res. 27 (2) (2020)
Yu-Chuan Chen, Jia-Yin Tu, Fu-Cheng Wang
Earthquake vibration control for buildings with inerter networks. ECC (2015)
Chung-Hao Lee, Yu-Chuan Chen, Fu-Cheng Wang
Earthquake suppression for a scale building model employing inclined inerter. SII (2015)
Mark Po-Hung Lin, Chih-Cheng Hsu, Yu-Chuan Chen
Clock-Tree Aware Multibit Flip-Flop Generation During Placement for Power Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (2) (2015)
Yu-Chuan Chen, Chih-Cheng Hsu, Mark Po-Hung Lin
Low-power gated clock tree optimization for three-dimensional integrated circuits. VLSI-DAT (2015)
Yu-Chuan Chen, Hyejung Ha, Hyunjoong Kim, Hongshik Ahn
Canonical Forest. Comput. Stat. 29 (3) (2014)
Chih-Cheng Hsu, Yu-Chuan Chen, Mark Po-Hung Lin
In-placement clock-tree aware multi-bit flip-flop generation for power optimization. ICCAD (2013)
Po-Hsun Wu, Mark Po-Hung Lin, Tung-Chieh Chen, Tsung-Yi Ho, Yu-Chuan Chen
Lithography-aware 1-dimensional cell generation. ECCTD (2013)
Po-Hsun Wu, Mark Po-Hung Lin, Tung-Chieh Chen, Tsung-Yi Ho, Yu-Chuan Chen, Shun-Ren Siao, Shu-Hung Lin
1-D Cell Generation With Printability Enhancement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (3) (2013)