Low-power gated clock tree optimization for three-dimensional integrated circuits.
Yu-Chuan ChenChih-Cheng HsuMark Po-Hung LinPublished in: VLSI-DAT (2015)
Keyphrases
- low power
- integrated circuit
- power consumption
- high speed
- three dimensional
- low cost
- high power
- single chip
- gate array
- low power consumption
- vlsi architecture
- power saving
- image sequences
- power reduction
- electron beam
- logic circuits
- digital signal processing
- x ray
- vlsi circuits
- image sensor
- mixed signal
- delay insensitive
- power dissipation
- cmos technology
- efficient implementation
- hardware description language
- nm technology
- general purpose