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Clock-Tree Aware Multibit Flip-Flop Generation During Placement for Power Optimization.
Mark Po-Hung Lin
Chih-Cheng Hsu
Yu-Chuan Chen
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2015)
Keyphrases
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power consumption
power dissipation
optimization problems
high speed
optimization algorithm
low power
optimal placement
flip flops
tree structure
duty cycle
multiple input
data structure
pattern recognition
index structure