Ching-Yu Chin

Publication Activity (10 Years)

Years Active: 2009-2017
Publications (10 Years): 3

Top Topics

Heterogeneous Databases

High Temperature

Finite Element Analysis

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Wan-Ning Wu, Chen Chen, Ching-Yu Chin, Chun-Kai Wang, Hung-Ming Chen
An analytical placer for heterogeneous FPGAs via rough-placed packing. VLSI-DAT (2017)
Chun-Kai Wang, Chuan-Chia Huang, Shih-Ying Sean Liu, Ching-Yu Chin, Sheng-Te Hu, Wei-Chen Wu, Hung-Ming Chen
Closing the Gap between Global and Detailed Placement: Techniques for Improving Routability. ISPD (2015)
Po-Cheng Pan, Ching-Yu Chin, Hung-Ming Chen, Tung-Chieh Chen, Chin-Chieh Lee, Jou-Chun Lin
A Fast Prototyping Framework for Analog Layout Migration With Planar Preservation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (9) (2015)
Chun-Kai Wang, Yeh-Chi Chang, Hung-Ming Chen, Ching-Yu Chin
Clock Tree Synthesis Considering Slew Effect on Supply Voltage Variation. ACM Trans. Design Autom. Electr. Syst. 20 (1) (2014)
Shih-Ying Sean Liu, Ren-Guo Luo, Suradeth Aroonsantidecha, Ching-Yu Chin, Hung-Ming Chen
Fast Thermal Aware Placement With Accurate Thermal Analysis Based on Green Function. IEEE Trans. Very Large Scale Integr. Syst. 22 (6) (2014)
Ching-Yu Chin, Chung-Yi Kuan, Tsung-Ying Tsai, Hung-Ming Chen, Yoji Kajitani
Escaped Boundary Pins Routing for High-Speed Boards. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (3) (2013)
Ching-Yu Chin, Po-Cheng Pan, Hung-Ming Chen, Tung-Chieh Chen, Jou-Chun Lin
Efficient analog layout prototyping by layout reuse with routing preservation. ICCAD (2013)
Suradeth Aroonsantidecha, Shih-Ying Liu, Ching-Yu Chin, Hung-Ming Chen
A fast thermal aware placement with accurate thermal analysis based on Green function. ASP-DAC (2012)
Tsung-Ying Tsai, Ren-Jie Lee, Ching-Yu Chin, Chung-Yi Kuan, Hung-Ming Chen, Yoji Kajitani
On routing fixed escaped boundary pins for high speed boards. DATE (2011)
Mango Chia-Tso Chao, Ching-Yu Chin, Yao-Te Tsou, Chi-Min Chang
A Novel Test Flow for One-Time-Programming Applications of NROM Technology. IEEE Trans. Very Large Scale Integr. Syst. 19 (12) (2011)
Mango Chia-Tso Chao, Ching-Yu Chin, Chen-Wei Lin
Mathematical yield estimation for two-dimensional-redundancy memory arrays. ICCAD (2010)
Ching-Yu Chin, Yao-Te Tsou, Chi-Min Chang, Mango Chia-Tso Chao
A novel test flow for one-time-programming applications of NROM technology. ITC (2009)
Mango Chia-Tso Chao, Hao-Yu Yang, Rei-Fu Huang, Shih-Chin Lin, Ching-Yu Chin
Fault models for embedded-DRAM macros. DAC (2009)