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Robust Chip-Level Clock Tree Synthesis.

Anand RajaramDavid Z. Pan
Published in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2011)
Keyphrases
  • high speed
  • tree structure
  • low cost
  • higher level
  • frequent patterns
  • robust estimation
  • computationally efficient
  • r tree
  • texture synthesis
  • levels of abstraction
  • vlsi implementation
  • program synthesis
  • analog vlsi