Joon-Sung Yang

Publication Activity (10 Years)

Years Active: 2007-2024
Publications (10 Years): 62

Top Topics

Dependency Analysis

Encoding Scheme

Energy Efficiency

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

IEICE Electron. Express

Publications

Thai-Hoang Nguyen, Muhammad Imran, Jaehyuk Choi, Joon-Sung Yang
HYDRA: A Hybrid Resistance Drift Resilient Architecture for Phase Change Memory-Based Neural Network Accelerators. IEEE Trans. Computers 73 (9) (2024)
Khanh-Binh Nguyen, Joon-Sung Yang
Boosting Semi-Supervised Learning by bridging high and low-confidence predictions. ICCV (Workshops) (2023)
Khanh-Binh Nguyen, Jaehyuk Choi, Joon-Sung Yang
EUNNet: Efficient UN-Normalized Convolution Layer for Stable Training of Deep Residual Networks Without Batch Normalization Layer. IEEE Access 11 (2023)
Insu Choi, Jae-Youn Hong, JaeHwa Jeon, Joon-Sung Yang
RQ-DNN: Reliable Quantization for Fault-tolerant Deep Neural Networks. DAC (2023)
Je-Woo Jang, Thai-Hoang Nguyen, Joon-Sung Yang
VECOM: Variation-Resilient Encoding and Offset Compensation Schemes for Reliable ReRAM-Based DNN Accelerator. ICCAD (2023)
Thai-Hoang Nguyen, Muhammad Imran, Jaehyuk Choi, Joon-Sung Yang
CRAFT: Criticality-Aware Fault-Tolerance Enhancement Techniques for Emerging Memories-Based Deep Neural Networks. CoRR (2023)
Hongju Kal, Hyoseong Choi, Ipoom Jeong, Joon-Sung Yang, Won Woo Ro
A convertible neural processor supporting adaptive quantization for real-time neural networks. J. Syst. Archit. 145 (2023)
Je-Woo Jang, Thai-Hoang Nguyen, Joon-Sung Yang
VECOM: Variation Resilient Encoding and Offset Compensation Schemes for Reliable ReRAM Based DNN Accelerator. CoRR (2023)
Thai-Hoang Nguyen, Muhammad Imran, Jaehyuk Choi, Joon-Sung Yang
CRAFT: Criticality-Aware Fault-Tolerance Enhancement Techniques for Emerging Memories-Based Deep Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (10) (2023)
Khanh-Binh Nguyen, Joon-Sung Yang
Boosting Semi-Supervised Learning by bridging high and low-confidence predictions. CoRR (2023)
JaeHwa Jeon, Jae-Youn Hong, Sunghoon Kim, Insu Choi, Joon-Sung Yang
PIE-DRAM: Postponing IECC to Enhance DRAM performance with access table. DAC (2023)
Youngkyoon Jang, Jiali Zheng, Jifei Song, Helisa Dhamo, Eduardo Pérez-Pellitero, Thomas Tanay, Matteo Maggioni, Richard Shaw, Sibi Catley-Chandar, Yiren Zhou, Jiankang Deng, Ruijie Zhu, Jiahao Chang, Ziyang Song, Jiahuan Yu, Tianzhu Zhang, Khanh-Binh Nguyen, Joon-Sung Yang, Andreea Dogaru, Bernhard Egger, Heng Yu, Aarush Gupta, Joel Julin, László A. Jeni, Hyeseong Kim, Jungbin Cho, Dosik Hwang, Deukhee Lee, Doyeon Kim, Dongseong Seo, SeungJin Jeon, YoungDon Choi, Jun Seok Kang, Ahmet Cagatay Seker, Sang Chul Ahn, Ales Leonardis, Stefanos Zafeiriou
VSCHH 2023: A Benchmark for the View Synthesis Challenge of Human Heads. ICCV (Workshops) (2023)
Suyong Lee, Insu Choi, Joon-Sung Yang
Bipolar vector classifier for fault-tolerant deep neural networks. DAC (2022)
Muhammad Imran, Taehyun Kwon, Nur A. Touba, Joon-Sung Yang
CEnT: An Efficient Architecture to Eliminate Intra-Array Write Disturbance in PCM. IEEE Trans. Computers 71 (5) (2022)
Khanh-Binh Nguyen, Jaehyuk Choi, Joon-Sung Yang
Checkerboard Dropout: A Structured Dropout With Checkerboard Pattern for Convolutional Neural Networks. IEEE Access 10 (2022)
Muhammad Imran, Taehyun Kwon, Joon-Sung Yang
ADAPT: A Write Disturbance-Aware Programming Technique for Scaled Phase Change Memory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (4) (2022)
Seo-Seok Lee, Joon-Sung Yang
Value-aware Parity Insertion ECC for Fault-tolerant Deep Neural Network. DATE (2022)
Thai-Hoang Nguyen, Muhammad Imran, Joon-Sung Yang
DynaPAT: A Dynamic Pattern-Aware Encoding Technique for Robust MLC PCM-Based Deep Neural Networks. ICCAD (2022)
Thai-Hoang Nguyen, Muhammad Imran, Jaehyuk Choi, Joon-Sung Yang
Low-Cost and Effective Fault-Tolerance Enhancement Techniques for Emerging Memories-Based Deep Neural Networks. DAC (2021)
Taehyun Kwon, Muhammad Imran, Joon-Sung Yang
Reliability Enhanced Heterogeneous Phase Change Memory Architecture for Performance and Energy Efficiency. IEEE Trans. Computers 70 (9) (2021)
Muhammad Imran, Hyunseung Han, Jooho Kim, Taehyun Kwon, Jaeyong Chung, Joon-Sung Yang
Virtualization-Based Efficient TSV Repair for 3-D Integrated Circuits. IEEE Access 8 (2020)
Taehyun Kwon, Muhammad Imran, Joon-Sung Yang
Pattern-Aware Encoding for MLC PCM Storage Density, Energy Efficiency, and Performance Enhancement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (9) (2020)
Taehyun Kwon, Muhammad Imran, Joon-Sung Yang
Cost-Effective Reliable MLC PCM Architecture Using Virtual Data Based Error Correction. IEEE Access 8 (2020)
Taehyun Kwon, Muhammad Imran, David Z. Pan, Joon-Sung Yang
Virtual-Tile-Based Flip-Flop Alignment Methodology for Clock Network Power Optimization. IEEE Trans. Very Large Scale Integr. Syst. 28 (5) (2020)
Inayat Ullah, Joon-Sung Yang, Jaeyong Chung
ER-TCAM: A Soft-Error-Resilient SRAM-Based Ternary Content-Addressable Memory for FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 28 (4) (2020)
Muhammad Imran, Taehyun Kwon, Joon-Sung Yang
Effective Write Disturbance Mitigation Encoding Scheme for High-density PCM. DATE (2020)
Inayat Ullah, Kashif Inayat, Joon-Sung Yang, Jaeyong Chung
Factored Radix-8 Systolic Array for Tensor Processing. DAC (2020)
Sangmok Jeong, SeungYup Kang, Joon-Sung Yang
PAIR: Pin-aligned In-DRAM ECC architecture using expandability of Reed-Solomon code. DAC (2020)
Jeong-Hyeon Kim, Ho-Jun Jo, Kyung-Kuk Jo, Sung-Hee Cho, Jaeyong Chung, Joon-Sung Yang
Reliable and Lightweight PUF-based Key Generation using Various Index Voting Architecture. DATE (2020)
Jung Min You, Joon-Sung Yang
MRLoc: Mitigating Row-hammering based on memory Locality. DAC (2019)
Yongshin Kang, Joon-Sung Yang, Jaeyong Chung
Weight Partitioning for Dynamic Fixed-Point Neuromorphic Computing Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (11) (2019)
Young-Min Lee, Joon-Sung Yang
Computation Offloading of Acoustic Model for Client-Edge-Based Speech-Recognition. CASES (work in progress) (2019)
Muhammad Imran, Taehyun Kwon, Jung Min You, Joon-Sung Yang
Flipcy: Efficient Pattern Redistribution for Enhancing MLC PCM Reliability and Storage Density. ICCAD (2019)
Jaeyong Chung, Taehwan Shin, Joon-Sung Yang
Simplifying Deep Neural Networks for FPGA-Like Neuromorphic Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (11) (2019)
Jae-San Kim, Joon-Sung Yang
DRIS-3: Deep Neural Network Reliability Improvement Scheme in 3D Die-Stacked Memory based on Fault Analysis. DAC (2019)
Taehyun Kwon, Muhammad Imran, Jung Min You, Joon-Sung Yang
Heterogeneous PCM array architecture for reliability, performance and lifetime enhancement. DATE (2018)
Taehee Lee, David Z. Pan, Joon-Sung Yang
Clock Network Optimization With Multibit Flip-Flop Generation Considering Multicorner Multimode Timing Constraint. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (1) (2018)
Sae-Eun Kim, Jaeyong Chung, Joon-Sung Yang
Mitigating Observability Loss of Toggle-Based X-Masking via Scan Chain Partitioning. IEEE Trans. Computers 67 (8) (2018)
Byung-Su Kim, Joon-Sung Yang
Bayesian theory based switching probability calculation method of critical timing path for on-chip timing slack monitoring. DATE (2018)
Hyunseung Han, Jaeyong Chung, Joon-Sung Yang
READ: Reliability Enhancement in 3D-Memory Exploiting Asymmetric SER Distribution. IEEE Trans. Computers 67 (8) (2018)
Seonbong Kim, Joon-Sung Yang
Optimized I/O determinism for emerging NVM-based NVMe SSD in an enterprise system. DAC (2018)
Byung-Su Kim, Joon-Sung Yang
System level performance analysis and optimization for the adaptive clocking based multi-core processor. ASP-DAC (2018)
Byung-Su Kim, Tae Hee Han, Joon-Sung Yang, Jaeyong Chung
New library development method by FSM based cell pattern extraction. IEICE Electron. Express 15 (9) (2018)
Hyunsu Chae, Joon-Sung Yang
-value elimination by scan slice correlation analysis. DAC (2018)
Taehee Lee, Joon-Sung Yang
Physical-aware gating element insertion for thermal-safe scan shift operation. IEICE Electron. Express 14 (7) (2017)
Taehee Lee, Nur A. Touba, Joon-Sung Yang
Enhancing Test Compression With Dependency Analysis for Multiple Expansion Ratios. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (9) (2017)
Chang-Hyun Oh, Sae-Eun Kim, Joon-Sung Yang
BIRA With Optimal Repair Rate Using Fault-Free Memory Region for Area Reduction. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2017)
Hyunseung Han, Nur A. Touba, Joon-Sung Yang
Exploiting Unused Spare Columns and Replaced Columns to Enhance Memory ECC. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (9) (2017)
Byung-Su Kim, Hyo-Sig Won, Tae Hee Han, Joon-Sung Yang
Non-linear library characterization method for FinFET logic cells by L1-minimization. ISCAS (2017)
Seung-Yeob Lee, Joon-Sung Yang
MVP ECC : Manufacturing process variation aware unequal protection ECC for memory reliability. DATE (2017)
Seonbong Kim, Joon-Sung Yang
Improving NVMe SSD I/O determinism with PCIe virtual channel: work-in-progress. CASES (2017)
So-Yeon Park, Sunil Lim, Dahee Jeong, Jungjin Lee, Joon-Sung Yang, HyungJune Lee
PUFSec: Device fingerprint-based security architecture for Internet of Things. INFOCOM (2017)
Chang-Hyun Oh, Sae-Eun Kim, Joon-Sung Yang
A BIRA using fault-free memory region for area reduction. APCCAS (2016)
Jin-Hyun Kang, Nur A. Touba, Joon-Sung Yang
Reducing control bit overhead for X-masking/X-canceling hybrid architecture via pattern partitioning. DAC (2016)
Jong Hyuk Park, Joon-Sung Yang
Memory ECC architecutre utilizing memory column spares. ISOCC (2016)
Taehee Lee, YongJoon Kim, Joon-Sung Yang
Temperature and voltage droop-aware test scheduling during scan shift operation. IEICE Electron. Express 13 (18) (2016)
Byung-Su Kim, Hyo-Sig Won, Tae Hee Han, Joon-Sung Yang
AFSEM: Advanced frequent subcircuit extraction method by graph mining approach for optimized cell library developments. ISCAS (2016)
Ik Joon Chang, Joon-Sung Yang
roll-off and inverse narrow-width effect. IEICE Electron. Express 13 (8) (2016)
Jung-Jin Lee, Joon-Sung Yang
System-level failure simulation and memory allocation scheme in 3D memory. APCCAS (2016)
Taehee Lee, JongWon Yi, Joon-Sung Yang
Multi-bit flip-flop generation considering multi-corner multi-mode timing constraint. ISCAS (2016)
Seung-Yeob Lee, Joon-Sung Yang
eFuse based IC authentication architecture. ISOCC (2016)
Joon-Sung Yang, Jinsuk Chung, Nur A. Touba
Enhancing Superset X-Canceling Method With Relaxed Constraints on Fault Observation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (2) (2016)
Byung-Jun Jang, Chan-Ho Lee, Sung-Hun Sim, Kyu-Won Choi, Do-Hun Byun, Yeon-Ho Jung, Ki-Man Park, Dong-Yeon Heo, Gyu-Hong Kim, Joon-Sung Yang
Robust via-programmable ROM design based on 45nm process considering process variation and enhancement Vmin and yield. ISCAS (2015)
Seongyeol Oh, Joon-Sung Yang, Andrea Bianchi, Hyoungshick Kim
Devil in a box: Installing backdoors in electronic door locks. PST (2015)
Hyunseung Han, Joon-Sung Yang
Asymmetric ECC organization in 3D-memory via spare column utilization. DFTS (2015)
Jaeyong Chung, Yonghyun Kim, Joon-Sung Yang
3-D Probe: Low-Cost Variation Modeling Using Intertest-Item Correlations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (12) (2014)
Chang Lin Li, Jae Hoon Lee, Joon-Sung Yang, Tae Hee Han
Communication-aware custom topology generation for VFI network-on-chip. IEICE Electron. Express 11 (18) (2014)
Joon-Sung Yang, Jinkyu Lee, Nur A. Touba
Utilizing ATE Vector Repeat With Linear Decompressor for Test Vector Compression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (8) (2014)
Junghwa Kim, Jun-Ho Huh, Soo-Yong Kim, Suk Won Kim, Joon-Sung Yang
Low-power shared memory architecture power mode for mobile system-on-chip. IEICE Electron. Express 11 (8) (2014)
Kihyuk Han, Joon-Sung Yang, Jacob A. Abraham
Enhanced algorithm of combining trace and scan signals in post-silicon validation. VTS (2013)
Joon-Sung Yang, Ik Joon Chang
Robust Buffered Clock Tree Synthesis by Sensitivity Based Link Insertion. IEICE Trans. Electron. (1) (2013)
Kihyuk Han, Joon-Sung Yang, Jacob A. Abraham
Dynamic Trace Signal Selection for Post-Silicon Validation. VLSI Design (2013)
Joon-Sung Yang, Nur A. Touba
Improved Trace Buffer Observation via Selective Data Capture Using 2-D Compaction for Post-Silicon Debug. IEEE Trans. Very Large Scale Integr. Syst. 21 (2) (2013)
Joon-Sung Yang, Nur A. Touba
Efficient Trace Signal Selection for Silicon Debug by Error Transmission Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (3) (2012)
Ik Joon Chang, Joon-Sung Yang
Bit-error rate improvement of TLC NAND Flash using state re-ordering. IEICE Electron. Express 9 (23) (2012)
Joon-Sung Yang, Nur A. Touba, Benoit Nadeau-Dostie
Test Point Insertion with Control Points Driven by Existing Functional Flip-Flops. IEEE Trans. Computers 61 (10) (2012)
Joon-Sung Yang, Nur A. Touba
X-Canceling MISR Architectures for Output Response Compaction With Unknown Values. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (9) (2012)
Joon-Sung Yang, Rudrajit Datta
Efficient Function Mapping in Nanoscale Crossbar Architecture. DFT (2011)
Joon-Sung Yang, Benoit Nadeau-Dostie, Nur A. Touba
Test point insertion using functional flip-flops to drive control points. ITC (2009)
Joon-Sung Yang, Nur A. Touba, Shih-Yu Yang, T. M. Mak
An industrial case study for X-canceling MISR. ITC (2009)
Joon-Sung Yang, Benoit Nadeau-Dostie, Nur A. Touba
Reducing Test Point Area for BIST through Greater Use of Functional Flip-Flops to Drive Control Points. DFT (2009)
Joon-Sung Yang, Nur A. Touba
Automated Selection of Signals to Observe for Efficient Silicon Debug. VTS (2009)
Joon-Sung Yang, Nur A. Touba
Enhancing Silicon Debug via Periodic Monitoring. DFT (2008)
Joon-Sung Yang, Nur A. Touba
Expanding Trace Buffer Observation Window for In-System Silicon Debug through Selective Capture. VTS (2008)
Joon-Sung Yang, Anand Rajaram, Ninghy Shi, Jian Chen, David Z. Pan
Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis. ISQED (2007)