​
Login / Signup
Hyunsu Chae
ORCID
Publication Activity (10 Years)
Years Active: 2004-2024
Publications (10 Years): 7
Top Topics
Optimum Design
Wimax Network
Machine Learning
Global Optimization
Top Venues
ISSCC
ASPDAC
ESSCIRC
DATE
</>
Publications
</>
Jahoon Jin
,
Soo-Min Lee
,
Kyunghwan Min
,
Sodam Ju
,
Jihoon Lim
,
Jisu Yook
,
Jihoon Lee
,
Hyunsu Chae
,
Kwonwoo Kang
,
Yunji Hong
,
Yeongcheol Jeong
,
Sungsik Park
,
Sang-Ho Kim
,
Jongwoo Lee
,
Joonsuk Kim
,
Sung-Ung Kwak
A 4-nm 16-Gb/s/pin Single-Ended PAM-4 Parallel Transceiver With Switching-Jitter Compensation and Transmitter Optimization.
IEEE J. Solid State Circuits
59 (1) (2024)
Hyunsu Chae
,
Keren Zhu
,
Bhyrav Mutnury
,
Zixuan Jiang
,
Daniel De Araujo
,
Douglas Wallace
,
Douglas Winterberg
,
Adam R. Klivans
,
David Z. Pan
ISOP-Yield: Yield-Aware Stack-Up Optimization for Advanced Package using Machine Learning.
ASPDAC
(2024)
Hyunsu Chae
,
Keren Zhu
,
Bhyrav Mutnury
,
Douglas Wallace
,
Douglas Winterberg
,
Daniel De Araujo
,
Jay Reddy
,
Adam R. Klivans
,
David Z. Pan
ISOP+: Machine Learning-Assisted Inverse Stack-Up Optimization for Advanced Package Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
43 (1) (2024)
Hyunsu Chae
,
Bhyrav Mutnury
,
Keren Zhu
,
Douglas Wallace
,
Douglas Winterberg
,
Daniel De Araujo
,
Jay Reddy
,
Adam R. Klivans
,
David Z. Pan
ISOP: Machine Learning-Assisted Inverse Stack-Up Optimization for Advanced Package Design.
DATE
(2023)
Jahoon Jin
,
Soo-Min Lee
,
Kyunghwan Min
,
Sodam Ju
,
Jihoon Lim
,
Hyunsu Chae
,
Kwonwoo Kang
,
Yunji Hong
,
Yeongcheol Jeong
,
Sang-Ho Kim
,
Jongwoo Lee
,
Joonsuk Kim
A 4nm 16Gb/s/pin Single-Ended PAM4 Parallel Transceiver with Switching-Jitter Compensation and Transmitter Optimization.
ISSCC
(2023)
Soo-Min Lee
,
Jihoon Lim
,
Jaehyuk Jang
,
Hyoungjoong Kim
,
Kyunghwan Min
,
Woongki Min
,
Hyeonji Han
,
Gyusik Kim
,
Jaeyoung Kim
,
Chulho Kim
,
Sejun Jeon
,
Jinhoon Park
,
Hyunsu Chae
,
Sangwook Han
,
Hiep Pham
,
Xingliang Zhao
,
Qilin Gu
,
Chih-Wei Yao
,
Sangho Kim
,
Jongwoo Lee
A 64Gb/s Downlink and 32Gb/s Uplink NRZ Wireline Transceiver with Supply Regulation, Background Clock Correction and EOM-based Channel Adaptation for Mid-Reach Cellular Mobile Interface in 8nm FinFET.
ESSCIRC
(2022)
Hyunsu Chae
,
Joon-Sung Yang
-value elimination by scan slice correlation analysis.
DAC
(2018)
Hyunsu Chae
,
Eun-Chul Park
,
Choong-Yul Cha
,
Jungeun Lee
,
Chun-Deok Suh
,
Jeongwook Koh
,
Hanseung Lee
,
Hoon-Tae Kim
A Fast Hopping Frequency Synthesizer for UWB Systems in a CMOS Technology.
ISWCS
(2005)
Jungeun Lee
,
Hyunsu Chae
,
Hanseung Lee
,
Maxim Konakov
,
Junghyun Lee
,
Jeongwon Lee
An improved architecture of the mixed mode clock/data recovery for DVD read channel.
CICC
(2004)
Maxim Konakov
,
Jae-Wook Lee
,
Junghyun Lee
,
Eun-Jin Ryu
,
Eingseob Cho
,
Jungeun Lee
,
Hyunsu Chae
,
Jeongwon Lee
High speed mixed analog/digital PRML architecture for optical data storage system.
SoCC
(2004)