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A 4nm 16Gb/s/pin Single-Ended PAM4 Parallel Transceiver with Switching-Jitter Compensation and Transmitter Optimization.

Jahoon JinSoo-Min LeeKyunghwan MinSodam JuJihoon LimHyunsu ChaeKwonwoo KangYunji HongYeongcheol JeongSang-Ho KimJongwoo LeeJoonsuk Kim
Published in: ISSCC (2023)
Keyphrases
  • optimization problems
  • high speed
  • optimization algorithm
  • global optimization
  • parallel processing
  • massively parallel