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A 4-nm 16-Gb/s/pin Single-Ended PAM-4 Parallel Transceiver With Switching-Jitter Compensation and Transmitter Optimization.

Jahoon JinSoo-Min LeeKyunghwan MinSodam JuJihoon LimJisu YookJihoon LeeHyunsu ChaeKwonwoo KangYunji HongYeongcheol JeongSungsik ParkSang-Ho KimJongwoo LeeJoonsuk KimSung-Ung Kwak
Published in: IEEE J. Solid State Circuits (2024)
Keyphrases
  • global optimization
  • parallel processing
  • high speed
  • optimization algorithm
  • evolutionary algorithm
  • multi objective
  • communication systems
  • constrained optimization