Yaojun Zhang

Publication Activity (10 Years)

Years Active: 2009-2023
Publications (10 Years): 15

Top Topics

Neural Network Training

Storage Systems

Surface Temperature

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Xiaoxi Wang, Yaojun Zhang, Danlin Yu
Exploring the Relationships between Land Surface Temperature and Its Influencing Factors Using Multisource Spatial Big Data: A Case Study in Beijing, China. Remote. Sens. 15 (7) (2023)
Yanjun Li, Chunshan Zu, Bingqian Wang, Zhenhua Zhu, Yaojun Zhang, Ran Duan, Bing Li, Bonan Yan
SRAM-Based Processing-In-Memory Design with Kullback-Leibler Divergence-Based Dynamic Precision Quantization. ACM Great Lakes Symposium on VLSI (2023)
Anjunyi Fan, Yihan Fu, Yaoyu Tao, Zhonghua Jin, Haiyue Han, Huiyu Liu, Yaojun Zhang, Bonan Yan, Yuchao Yang, Ru Huang
Hadamard product-based in-memory computing design for floating point neural network training. Neuromorph. Comput. Eng. 3 (1) (2023)
Yaojun Zhang, Lanpeng Ji, Georgios Aivaliotis, Charles Taylor
Bayesian CART models for insurance claims frequency. CoRR (2023)
Anjunyi Fan, Bo Hu, Zhonghua Jin, Haiyue Han, Yaojun Zhang, Yue Yang, Yuchao Yang, Bonan Yan, Ru Huang
Live Demonstration: SRAM Compute-In-Memory Based Visual & Aural Recognition System. AICAS (2023)
Kangyi Qiu, Yaojun Zhang, Bonan Yan, Ru Huang
Heterogeneous Memory Architecture Accommodating Processing-in-Memory on SoC for AIoT Applications. ASP-DAC (2022)
Bonan Yan, Jeng-Long Hsu, Pang-Cheng Yu, Chia-Chi Lee, Yaojun Zhang, Wenshuo Yue, Guoqiang Mei, Yuchao Yang, Yue Yang, Hai Li, Yiran Chen, Ru Huang
27.38-TOPS/W Signed-INT8 Dynamic-Logic-Based ADC-less SRAM Compute-in-Memory Macro in 28nm with Reconfigurable Bitwise Operation for AI and Embedded Applications. ISSCC (2022)
Yaojun Zhang, Gilbert M. Tumibay
Stock Market Prediction Model Based on LSTM Deep Learning: The Case of Top Corporate Company in China. AIAM (2022)
Bonan Yan, Fan Chen, Yaojun Zhang, Chang Song, Hai Li, Yiran Chen
Exploring the opportunity of implementing neuromorphic computing systems with spintronic devices. DATE (2018)
Yaojun Zhang, Bonan Yan, Xiaobin Wang, Yiran Chen
Persistent and Nonpersistent Error Optimization for STT-RAM Cell Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (7) (2017)
Enes Eken, Ismail Bayram, Yaojun Zhang, Bonan Yan, Wenqing Wu, Hai (Helen) Li, Yiran Chen
Giant Spin-Hall assisted STT-RAM and logic design. Integr. 58 (2017)
Mengjie Mao, Wujie Wen, Yaojun Zhang, Yiran Chen, Hai Li
An Energy-Efficient GPGPU Register File Architecture Using Racetrack Memory. IEEE Trans. Computers 66 (9) (2017)
Enes Eken, Ismail Bayram, Yaojun Zhang, Bonan Yan, Wenqing Wu, Hai (Helen) Li, Yiran Chen
Spin-Hall Assisted STT-RAM Design and Discussion. SLIP (2016)
Xian Zhang, Guangyu Sun, Yaojun Zhang, Yiran Chen, Hai Li, Wujie Wen, Jia Di
A novel PUF based on cell error rate distribution of STT-RAM. ASP-DAC (2016)
Jianlei Yang, Peiyuan Wang, Yaojun Zhang, Yuanqing Cheng, Weisheng Zhao, Yiran Chen, Hai (Helen) Li
Radiation-Induced Soft Error Analysis of STT-MRAM: A Device to Circuit Approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (3) (2016)
Bonan Yan, Yaojun Zhang, Enes Eken, Wujie Wen, Weisheng Zhao, Yiran Chen
Recent progresses of STT memory design and applications. ASICON (2015)
Yaojun Zhang, Bonan Yan, Wenqing Wu, Hai Li, Yiran Chen
Giant spin hall effect (GSHE) logic design for low power application. DATE (2015)
Yaojun Zhang, Yong Li, Zhenyu Sun, Hai Li, Yiran Chen, Alex K. Jones
Read Performance: The Newest Barrier in Scaled STT-RAM. IEEE Trans. Very Large Scale Integr. Syst. 23 (6) (2015)
Bonan Yan, Zheng Li, Yaojun Zhang, Jianlei Yang, Hai Li, Weisheng Zhao, Pierre Chor-Fung Chia
A High-Speed Robust NVM-TCAM Design Using Body Bias Feedback. ACM Great Lakes Symposium on VLSI (2015)
Enes Eken, Yaojun Zhang, Wujie Wen, Rajiv V. Joshi, Hai Li, Yiran Chen
A New Field-assisted Access Scheme of STT-RAM with Self-reference Capability. DAC (2014)
Wujie Wen, Yaojun Zhang, Yiran Chen, Yu Wang, Yuan Xie
PS3-RAM: A Fast Portable and Scalable Statistical STT-RAM Reliability/Energy Analysis Method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (11) (2014)
Xiaoxiao Liu, Yong Li, Yaojun Zhang, Alex K. Jones, Yiran Chen
STD-TLB: A STT-RAM-based dynamically-configurable translation lookaside buffer for GPU architectures. ASP-DAC (2014)
Wujie Wen, Yaojun Zhang, Mengjie Mao, Yiran Chen
State-Restrict MLC STT-RAM Designs for High-Reliable High-Performance Memory System. DAC (2014)
Mengjie Mao, Wujie Wen, Yaojun Zhang, Yiran Chen, Hai (Helen) Li
Exploration of GPGPU Register File Architecture Using Domain-wall-shift-write based Racetrack Memory. DAC (2014)
Yong Li, Yaojun Zhang, Hai Li, Yiran Chen, Alex K. Jones
C1C: A configurable, compiler-guided STT-RAM L1 cache. ACM Trans. Archit. Code Optim. 10 (4) (2013)
Yaojun Zhang, Lu Zhang, Yiran Chen
MLC STT-RAM design considering probabilistic and asymmetric MTJ switching. ISCAS (2013)
Bin Li, Baolei Li, Yang Mo, Yaojun Zhang
Pseudo-Three-Dimensional Navigation in Helical Scan Security Inspection. ICIG (2013)
Jie Guo, Wujie Wen, Yaojun Zhang, Sicheng Li, Hai Li, Yiran Chen
DA-RAID-5: a disturb aware data protection technique for NAND flash storage systems. DATE (2013)
Wujie Wen, Yaojun Zhang, Lu Zhang, Yiran Chen
Loadsa: A yield-driven top-down design method for STT-RAM array. ASP-DAC (2013)
Yaojun Zhang, Ismail Bayram, Yu Wang, Hai Li, Yiran Chen
ADAMS: asymmetric differential STT-RAM cell structure for reliable and high-performance applications. ICCAD (2013)
Yiran Chen, Weng-Fai Wong, Hai Li, Cheng-Kok Koh, Yaojun Zhang, Wujie Wen
On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations. ACM J. Emerg. Technol. Comput. Syst. 9 (2) (2013)
Yaojun Zhang, Lu Zhang, Wujie Wen, Guangyu Sun, Yiran Chen
Multi-level cell STT-RAM: Is it realistic or just a dream? ICCAD (2012)
Guangyu Sun, Yaojun Zhang, Yu Wang, Yiran Chen
Improving energy efficiency of write-asymmetric memories by log style write. ISLPED (2012)
Yaojun Zhang, Xiaobin Wang, Yong Li, Alex K. Jones, Yiran Chen
Asymmetry of MTJ switching and its implication to STT-RAM designs. DATE (2012)
Yong Li, Yaojun Zhang, Yiran Chen, Alex K. Jones
Combating Write Penalties Using Software Dispatch for On-Chip MRAM Integration. IEEE Embed. Syst. Lett. 4 (4) (2012)
Yiran Chen, Yaojun Zhang, Peiyuan Wang
Probabilistic design in spintronic memory and logic circuit. ASP-DAC (2012)
Wujie Wen, Yaojun Zhang, Yiran Chen, Yu Wang, Yuan Xie
PS3-RAM: a fast portable and scalable statistical STT-RAM reliability analysis method. DAC (2012)
Zhongyuan Chen, Yuru Zhang, Dangxiao Wang, Chaobin Li, Yaojun Zhang
iFeel6-BH1500: A large-scale 6-DOF haptic device. VECIMS (2012)
Zhenyu Sun, Xiang Chen, Yaojun Zhang, Hai Li, Yiran Chen
Nonvolatile Memories as the Data Storage System for Implantable ECG Recorder. ACM J. Emerg. Technol. Comput. Syst. 8 (2) (2012)
Yaojun Zhang, Xiaobin Wang, Yiran Chen
STT-RAM cell design optimization for persistent and non-persistent error rate reduction: A statistical design view. ICCAD (2011)
Hao Hu, Yuru Zhang, Xiaowei Dai, Yaojun Zhang
The analysis of resolution for cable-driven haptic device. ROBIO (2010)
Yaojun Zhang, Yuru Zhang, Xiaowei Dai, Yi Yang
Workspace analysis of a novel 6-dof cable-driven parallel robot. ROBIO (2009)