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On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations.
Yiran Chen
Weng-Fai Wong
Hai Li
Cheng-Kok Koh
Yaojun Zhang
Wujie Wen
Published in:
ACM J. Emerg. Technol. Comput. Syst. (2013)
Keyphrases
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memory access
random access memory
analog vlsi
low cost
high speed
data access
dynamic model
real time
data management
external forces
control scheme
knowledge transfer
high density
design considerations
physical design
host computer
single chip
shared memory
control algorithm
closed loop
neural network