Mengjie Mao

Publication Activity (10 Years)

Years Active: 2010-2021
Publications (10 Years): 11

Top Topics

Cache Management

Heterogeneous Computing

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Xiaoxiao Liu, Mengjie Mao, Xiuyuan Bi, Hai Helen Li, Yiran Chen
Exploring Applications of STT-RAM in GPU Architectures. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (1) (2021)
Bing Li, Mengjie Mao, Xiaoxiao Liu, Tao Liu, Zihao Liu, Wujie Wen, Yiran Chen, Hai (Helen) Li
Thread Batching for High-performance Energy-efficient GPU Memory Design. ACM J. Emerg. Technol. Comput. Syst. 15 (4) (2019)
Bing Li, Mengjie Mao, Xiaoxiao Liu, Tao Liu, Zihao Liu, Wujie Wen, Yiran Chen, Hai Helen Li
Thread Batching for High-performance Energy-efficient GPU Memory Design. CoRR (2019)
Zihao Liu, Mengjie Mao, Tao Liu, Xue Wang, Wujie Wen, Yiran Chen, Hai Li, Danghui Wang, Yukui Pei, Ning Ge
TriZone: A Design of MLC STT-RAM Cache for Combined Performance, Energy, and Reliability Optimizations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (10) (2018)
Xiuyuan Bi, Mengjie Mao, Danghui Wang, Hai Helen Li
Cross-Layer Optimization for Multilevel Cell STT-RAM Caches. IEEE Trans. Very Large Scale Integr. Syst. 25 (6) (2017)
Mengjie Mao, Wujie Wen, Yaojun Zhang, Yiran Chen, Hai Li
An Energy-Efficient GPGPU Register File Architecture Using Racetrack Memory. IEEE Trans. Computers 66 (9) (2017)
Mengjie Mao, Wujie Wen, Xiaoxiao Liu, Jingtong Hu, Danghui Wang, Yiran Chen, Hai Li
TEMP: thread batch enabled memory partitioning for GPU. DAC (2016)
Sicheng Li, Xiaoxiao Liu, Mengjie Mao, Hai (Helen) Li, Yiran Chen, Boxun Li, Yu Wang
Heterogeneous systems with reconfigurable neuromorphic computing accelerators. ISCAS (2016)
Wujie Wen, Mengjie Mao, Hai Li, Yiran Chen, Yukui Pei, Ning Ge
A holistic tri-region MLC STT-RAM design with combined performance, energy, and reliability optimizations. DATE (2016)
Xue Wang, Mengjie Mao, Enes Eken, Wujie Wen, Hai Li, Yiran Chen
Sliding Basket: An adaptive ECC scheme for runtime write failure suppression of STT-RAM cache. DATE (2016)
Xiaoxiao Liu, Mengjie Mao, Beiye Liu, Boxun Li, Yu Wang, Hao Jiang, Mark Barnell, Qing Wu, Jianhua Joshua Yang, Hai Li, Yiran Chen
Harmonica: A Framework of Heterogeneous Computing Systems With Memristor-Based Neuromorphic Computing Accelerators. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2016)
Xiaoxiao Liu, Mengjie Mao, Xiuyuan Bi, Hai Li, Yiran Chen
An efficient STT-RAM-based register file in GPU architectures. ASP-DAC (2015)
Hai Li, Beiye Liu, Xiaoxiao Liu, Mengjie Mao, Yiran Chen, Qing Wu, Qinru Qiu
The applications of memristor devices in next-generation cortical processor designs. ISCAS (2015)
Mengjie Mao, Jingtong Hu, Yiran Chen, Hai Li
VWS: a versatile warp scheduler for exploring diverse cache localities of GPGPU applications. DAC (2015)
Xiaoxiao Liu, Mengjie Mao, Beiye Liu, Hai Li, Yiran Chen, Boxun Li, Yu Wang, Hao Jiang, Mark Barnell, Qing Wu, Jianhua Joshua Yang
RENO: a high-efficient reconfigurable neuromorphic computing accelerator design. DAC (2015)
Mengjie Mao, Guangyu Sun, Yong Li, Alex K. Jones, Yiran Chen
Prefetching techniques for STT-RAM based last-level cache in CMP systems. ASP-DAC (2014)
Xiaoxiao Liu, Mengjie Mao, Hai Li, Yiran Chen, Hao Jiang, J. Joshua Yang, Qing Wu, Mark Barnell
A heterogeneous computing system with memristor-based neuromorphic accelerators. HPEC (2014)
Hai Li, Miao Hu, Xiaoxiao Liu, Mengjie Mao, Chuandong Li, Shukai Duan
Emerging memristor technology enabled next generation cortical processor. SoCC (2014)
Wujie Wen, Yaojun Zhang, Mengjie Mao, Yiran Chen
State-Restrict MLC STT-RAM Designs for High-Reliable High-Performance Memory System. DAC (2014)
Mengjie Mao, Wujie Wen, Yaojun Zhang, Yiran Chen, Hai (Helen) Li
Exploration of GPGPU Register File Architecture Using Domain-wall-shift-write based Racetrack Memory. DAC (2014)
Hai Li, Xiaoxiao Liu, Mengjie Mao, Yiran Chen, Qing Wu, Mark Barnell
Neuromorphic hardware acceleration enabled by emerging technologies (Invited paper). ISIC (2014)
Wujie Wen, Mengjie Mao, Xiaochun Zhu, Seung H. Kang, Danghui Wang, Yiran Chen
CD-ECC: content-dependent error correction codes for combating asymmetric nonvolatile memory operation errors. ICCAD (2013)
Mengjie Mao, Hai (Helen) Li, Alex K. Jones, Yiran Chen
Coordinating prefetching and STT-RAM based last-level cache management for multicore systems. ACM Great Lakes Symposium on VLSI (2013)
Xiuyuan Bi, Mengjie Mao, Danghui Wang, Hai Li
Unleashing the potential of MLC STT-RAM caches. ICCAD (2013)
Mengjie Mao, Hong An, Tao Sun, Qi Li, Bobin Deng, Xuechao Wei, Junrui Zhou
Distributed Control Independence for Composable Multi-processors. ACIS-ICIS (2012)
Mengjie Mao, Hong An, Bobin Deng, Tao Sun, Xuechao Wei, Wei Zhou, Wenting Han
Distributed replay protocol for distributed uniprocessors. ICS (2012)
Bobin Deng, Hong An, Qi Li, Gongming Li, Mengjie Mao
Value Predicted LogSPoTM: Improve the Parallesim of Thread Level System by Using a Value Predictor. ACIS-ICIS (2012)
Tao Sun, Hong An, Yongqing Ren, Mengjie Mao, Yang Liu, Mu Xu, Qi Li
FACRA: Flexible-Core Architecture Chip Resource Abstractor. PDCAT (2010)