Xiuyuan Bi

Publication Activity (10 Years)

Years Active: 2011-2021
Publications (10 Years): 6

Top Topics

Design Methodology

Garbage Collection

Data Management

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Xiaoxiao Liu, Mengjie Mao, Xiuyuan Bi, Hai Helen Li, Yiran Chen
Exploring Applications of STT-RAM in GPU Architectures. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (1) (2021)
Xiuyuan Bi, Mengjie Mao, Danghui Wang, Hai Helen Li
Cross-Layer Optimization for Multilevel Cell STT-RAM Caches. IEEE Trans. Very Large Scale Integr. Syst. 25 (6) (2017)
Zhenyu Sun, Xiuyuan Bi, Wenqing Wu, Sungjoo Yoo, Hai (Helen) Li
Array Organization and Data Management Exploration in Racetrack Memory. IEEE Trans. Computers 65 (4) (2016)
Zheng Li, Xiuyuan Bi, Hai (Helen) Li, Yiran Chen, Jianying Qin, Peng Guo, Wenjie Kong, Wenshan Zhan, Xiufeng Han, Hong Zhang, Lingling Wang, Guanping Wu, Hanming Wu
Design and Implementation of a 4Kb STT-MRAM with Innovative 200nm Nano-ring Shaped MTJ. ISLPED (2016)
Hai (Helen) Li, Xiuyuan Bi, Zhenyu Sun
The evolutionary spintronic technologies and their usage in high performance computing. SoCC (2015)
Xiaoxiao Liu, Mengjie Mao, Xiuyuan Bi, Hai Li, Yiran Chen
An efficient STT-RAM-based register file in GPU architectures. ASP-DAC (2015)
Zhenyu Sun, Xiuyuan Bi, Alex K. Jones, Hai Li
Design exploration of racetrack lower-level caches. ISLPED (2014)
Jianxing Wang, Pooja Roy, Weng-Fai Wong, Xiuyuan Bi, Hai Li
Optimizing MLC-based STT-RAM caches by dynamic block size reconfiguration. ICCD (2014)
Zhenyu Sun, Xiuyuan Bi, Hai Li, Weng-Fai Wong, Xiaochun Zhu
STT-RAM Cache Hierarchy With Multiretention MTJ Designs. IEEE Trans. Very Large Scale Integr. Syst. 22 (6) (2014)
Xiuyuan Bi, Mohamed Anis Weldon, Hai Li
STT-RAM designs supporting dual-port accesses. DATE (2013)
Zhijie Chen, Lu Zhang, Xiuyuan Bi, Hai Li
A pseudo-weighted sensing scheme for memristor based cross-point memory. NANOARCH (2013)
Xiuyuan Bi, Mengjie Mao, Danghui Wang, Hai Li
Unleashing the potential of MLC STT-RAM caches. ICCAD (2013)
Xiuyuan Bi, Zhenyu Sun, Hai Li, Wenqing Wu
Probabilistic design methodology to improve run-time stability and performance of STT-RAM caches. ICCAD (2012)
Zhenyu Sun, Xiuyuan Bi, Hai Li
Process variation aware data management for STT-RAM cache design. ISLPED (2012)
Xiuyuan Bi, Chao Zhang, Hai Li, Yiran Chen, Robinson E. Pino
Spintronic memristor based temperature sensor design with CMOS current reference. DATE (2012)
Xiuyuan Bi, Hai Li, Jae-Joon Kim
Analysis and Optimization of Thermal Effect on STT-RAM Based 3-D Stacked Cache Design. ISVLSI (2012)
Zhenyu Sun, Xiuyuan Bi, Hai (Helen) Li, Weng-Fai Wong, Zhong-Liang Ong, Xiaochun Zhu, Wenqing Wu
Multi retention level STT-RAM cache designs with a dynamic refresh scheme. MICRO (2011)