Seung H. Kang

Publication Activity (10 Years)

Years Active: 2009-2018
Publications (10 Years): 2

Top Topics

Design Considerations

Error Correction

Top Venues

IEEE J. Emerg. Sel. Topics Circuits Syst.

IEEE Trans. Multi Scale Comput. Syst.

Publications

Linuo Xue, Bi Wu, Beibei Zhang, Yuanqing Cheng, Peiyuan Wang, Chando Park, Jimmy J. Kan, Seung H. Kang, Yuan Xie
An Adaptive 3T-3MTJ Memory Cell Design for STT-MRAM-Based LLCs. IEEE Trans. Very Large Scale Integr. Syst. 26 (3) (2018)
Ping Chi, Shuangchen Li, Yuanqing Cheng, Yu Lu, Seung H. Kang, Yuan Xie
Architecture design with STT-RAM: Opportunities and challenges. ASP-DAC (2016)
Cong Xu, Yang Zheng, Dimin Niu, Xiaochun Zhu, Seung H. Kang, Yuan Xie
Impact of Write Pulse and Process Variation on 22 nm FinFET-Based STT-RAM Design: A Device-Architecture Co-Optimization Approach. IEEE Trans. Multi Scale Comput. Syst. 1 (4) (2015)
Kangho Lee, Jimmy J. Kan, Seung H. Kang
Unified embedded non-volatile memory for emerging mobile markets. ISLPED (2014)
Wujie Wen, Mengjie Mao, Xiaochun Zhu, Seung H. Kang, Danghui Wang, Yiran Chen
CD-ECC: content-dependent error correction codes for combating asymmetric nonvolatile memory operation errors. ICCAD (2013)
Wenqing Wu, Xiaochun Zhu, Seung H. Kang, Kendrick Yuen, Rob Gilmore
Probabilistically Programmed STT-MRAM. IEEE J. Emerg. Sel. Topics Circuits Syst. 2 (1) (2012)
Peiyuan Wang, Xiang Chen, Yiran Chen, Hai Li, Seung H. Kang, Xiaochun Zhu, Wenqing Wu
A 1.0V 45nm nonvolatile magnetic latch design and its robustness analysis. CICC (2011)
Cong Xu, Dimin Niu, Xiaochun Zhu, Seung H. Kang, Matt Nowak, Yuan Xie
Device-architecture co-optimization of STT-RAM based memory for low power embedded systems. ICCAD (2011)
Xia Li, Wei Zhao, Yu Cao, Zhi Zhu, Jooyoung Song, David Bang, Chi-Chao Wang, Seung H. Kang, Joseph Wang, Matt Nowak, Nick Yu
Pathfinding for 22nm CMOS designs using Predictive Technology Models. CICC (2009)